FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 177

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note 1: A logical device will be active and powered up according to the following equation:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or
clears the other.
Note: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical
Device I/O map, then read or write is not valid and is ignored.
Note 2. The activate bit for Logical Device 5 (Serial Port 2) is reset on Vtr POR only.
DMA Channel Select
Default = 0x04
on Vcc POR or
Reset_Drv
32-Bit Memory
Space Configuration
Logical Device
Logical Device
Config.
Reserved
LOGICAL DEVICE
REGISTER
(0xA9-0xDF)
(0xE0-0xFE)
(0x76-0xA8)
(0x71,0x73)
(0x74,0x75)
ADDRESS
0xFF
Reserved - not implemented.
locations ignore writes and return zero when read.
Only 0x74 is implemented for FDC, Serial Port 2 and
Parallel port. 0x75 is not implemented and ignores
writes and returns zero when read. Refer to DMA
Channel Configuration.
Reserved - not implemented.
locations ignore writes and return zero when read.
Reserved - not implemented.
locations ignore writes and return zero when read.
Reserved - Vendor Defined (see SMSC defined
Logical Device Configuration Registers)
Reserved
180
DESCRIPTION
These register
These register
These register
STATE
C
C
C
C