ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 12

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1160-01_7
Product data sheet
Fig 9.
Internal FIFO buffer RAM access cycle.
8.5 FIFO buffer RAM access by DMA mode
write command
(16 bits)
Figure 9
cycle, the microprocessor first writes the FIFO buffer RAM’s command code to the
command port, and then writes the data words one by one to the data port until half of the
transfer’s byte count is reached. The HcTransferCounter register (22H to read, A2H to
write) is used to specify the byte count of a FIFO buffer RAM’s read cycle or write cycle.
Every access cycle must be in the same access direction. The read cycle procedure is
similar to the write cycle.
The DMA interface between a microprocessor and the ISP1160/01 is shown in
When doing a DMA transfer, at the beginning of every burst the ISP1160/01 outputs a
DMA request to the microprocessor via pin DREQ. After receiving this signal, the
microprocessor will reply with a DMA acknowledge to the ISP1160/01 via pin DACK_N,
and at the same time, execute the DMA transfer through the data bus. In the DMA mode,
the microprocessor must issue a read or write signal to the ISP1160/01’s pins RD_N or
WR_N. The ISP1160/01 will repeat the DMA cycles until it receives an EOT signal to
terminate the DMA transfer.
The ISP1160/01 supports both external and internal EOT signals. The external EOT
signal is received as input on pin EOT, and generally comes from the external
microprocessor. The internal EOT signal is generated inside the ISP1160/01.
To select either EOT method, set the appropriate DMA configuration register (see
Section
HcDMAConfiguration register (21H to read, A1H to write) to logic 1 will enable the DMA
counter for DMA transfer. When the DMA counter reaches the value of the
HcTransferCounter register, the internal EOT signal will be generated to terminate the
DMA transfer.
The ISP1160/01 supports either single-cycle DMA operation or burst mode DMA
operation; see
10.4.2). For example, setting DMACounterSelect (bit 2) of the
shows a complete access cycle of the HC internal FIFO buffer RAM. For a write
Figure 10
FIFO buffer RAM access cycle (transfer counter = 2N)
read/write data
#1 (16 bits)
Rev. 07 — 29 September 2009
and
Figure
read/write data
11.
#2 (16 bits)
Embedded USB host controller
read/write data
#N (16 bits)
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
MGT941
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Figure
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4.