ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 41

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 16.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
reserved
R/W
R/W
R/W
R/W
MIE
31
23
15
0
0
0
7
0
Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Code (Hex): 04 — read
Code (Hex): 84 — write
Table 17.
Bit
31
30 to 7
6
5
4
3
•
•
•
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
Bit MasterInterruptEnable is set.
RHSC
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
HcInterruptEnable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 07 — 29 September 2009
Description
MasterInterruptEnable by the HCD: A logic 0 is ignored by the HC. A
logic 1 enables interrupt generation by events specified in other bits of
this register.
reserved
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
0 — ignore
1 — enable interrupt generation due to frame Number Overflow
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
0 — ignore
1 — enable interrupt generation due to Resume Detect
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
reserved
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
Embedded USB host controller
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
ISP1160/01
reserved
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
R/W
R/W
R/W
R/W
SO
24
16
0
0
8
0
0
0
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