ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 60

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 44.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcμPInterruptEnable register: bit allocation
10.5.1 HcChipID register (R: 27H)
reserved
10.5 HC miscellaneous registers
R/W
R/W
15
0
7
0
Table 45.
Read this register to get the ID of the ISP1160/01 silicon chip. The higher byte stands for
the product name. The lower byte indicates the revision number of the product including
engineering samples.
Code (Hex): 27 — read
Bit
15 to 7
6
5
4
3
2
1
0
ClkReady
R/W
R/W
14
0
6
0
HcμPInterruptEnable register: bit description
Symbol
-
ClkReady
HC
Suspended
Enable
OPR
Interrupt
Enable
-
EOT
Interrupt
Enable
ATL
Interrupt
Enable
SOF
Interrupt
Enable
Suspended
Enable
R/W
R/W
HC
13
0
5
0
Rev. 07 — 29 September 2009
Description
reserved
0 — power-up value
1 — enables ClkReady interrupt
0 — power-up value
1 — enables HC suspended interrupt. When the microprocessor
wants to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are suspended,
then the HC stops sending SOF; the HC is suspended by having the
HcControl register written into.
0 — power-up value
1 — enables the 32-bit operational register’s interrupt (if the HC
requires the operational register to be updated)
reserved
0 — power-up value
1 — enables the EOT interrupt which indicates an end of a read/write
transfer
0 — power-up value
1 — enables ATL interrupt. The time for this interrupt depends on the
number of clock bits set for USB activities in each ms.
0 — power-up value
1 — enables the interrupt bit due to SOF (for the microprocessor DMA
to get ISO data from the HC by first accessing the
HcDMAConfiguration register)
Interrupt
Enable
OPR
R/W
R/W
12
0
4
0
reserved
reserved
R/W
R/W
11
0
3
0
Interrupt
Enable
Embedded USB host controller
EOT
R/W
R/W
10
0
2
0
ISP1160/01
Interrupt
Enable
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
ATL
9
0
1
0
Interrupt
Enable
SOF
R/W
R/W
8
0
0
0
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