ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 17

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1160-01_7
Product data sheet
Fig 15. ISP1160/01 HC USB transaction loop.
Initialize
Reset
Entry
9.2 Generating USB traffic
HC
The USB states are reflected in the HostControllerFunctionalState field of the HcControl
register (01H to read, 81H to write), which is located at bits 7 and 6 of the register.
The HCD can perform only the USB state transitions shown in
Remark: The Software Reset in
command. It is caused by the HostControllerReset field of the HcCommandStatus register
(02H to read, 82H to write).
USB traffic can be generated only when the ISP1160/01 USB HC is in the
USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState
field of the HcControl register before generating USB traffic.
A simplistic flow diagram showing when and how to generate USB traffic is shown in
Figure
for the USB protocol and the ISP1160/01 USB HC’s register usage.
Description of
1. Reset: This includes hardware reset by pin RESET_N and software reset by the
2. Initialize HC: It includes:
USBOperational
HC state =
HcSoftwareReset command (A9H). The reset function will clear all the HC’s internal
control registers to their reset status. After reset, the HCD must initialize the
ISP1160/01 USB HC by setting some registers.
a. Setting the physical size for the HC’s internal FIFO buffer RAM by setting the
b. Setting the HcHardwareConfiguration register according to requirements.
c. Clearing interrupt events, if required.
d. Enabling interrupt events, if required.
e. Setting the HcFmInterval register (0DH to read, 8DH to write).
f. Setting the HC’s Root Hub registers.
g. Setting the HcControl register to move the HC into the USBOperational state.
See also
15. For greater accuracy, refer to the Universal Serial Bus Specification Rev. 2.0
HcITLBufferLength register (2AH to read, AAH to write) and the
HcATLBufferLength register (2BH to read, ABH to write).
Section
Figure
HC informs HCD of
USB traffic results
USB traffic?
Need
Exit
Rev. 07 — 29 September 2009
15:
9.5.
no
yes
Figure 14
HC performs USB transactions
Prepare PTD data in
μP system RAM
via USB bus I/F
is not caused by the HcSoftwareReset
Transfer PTD data into
Embedded USB host controller
HC FIFO buffer RAM
HC interprets
Figure
PTD data
ISP1160/01
MGT948
© ST-ERICSSON 2009. All rights reserved.
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