ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 68

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

13. Power-on reset (POR)
ISP1160-01_7
Product data sheet
When V
be typically (600 ns to 1000 ns) + X, when V
V
supply circuit.
To give a better view of the functionality,
with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, < 11 μs), the internal POR
pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the
detector will see the passing of the trip level and a delay element will add another t
before it drops to 0.
The internal POR pulse will be generated whenever V
than 11 μs.
Even if V
on-chip voltage regulator ensure that 3.3 V is going to the internal POR circuitry by
clipping the voltage above 3.3 V.
The RESET_N pin can be either connected to V
externally controlled (by the microprocessor, ASIC, and so on).
availability of the clock with respect to the external POR.
Fig 33. Internal POR timing.
Fig 34. Clock with respect to the external POR.
CC
is rising with respect to V
t0
CC
CC
(1) PORP = power-on reset pulse.
Stable external clock is available at A.
is directly connected to the RESET_N pin, the internal pulse width (t
is 5.0 V, V
t1
t
PORP
Rev. 07 — 29 September 2009
trip
EXTERNAL CLOCK
still remains at 2.03 V. This is because the 5 V tolerant pads and
trip
(2.03 V). The time X is decided by the external power
POR
t2
Figure 33
CC
t3
is 3.3 V. The time X depends on how fast
t
CC
PORP
A
shows a possible curve of V
(using the internal POR circuit) or
CC(POR)
Embedded USB host controller
t4
004aaa365
drops below V
t5
Figure 34
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
shows the
trip
004aaa389
PORP
V
V
BAT(POR)
trip
CC(POR)
PORP
for more
(1)
PORP
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) will