PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 176

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
request need not be of exactly the same type that is al-
ready in progress.
Table 11-14. IntE bit functions
IE (ICP DMA enable).This bit is must be set to ’1’ to allow
the ICP to write pixel data through the PCI interface. If
this bit is cleared to ’0’, the ICP is not allowed to use the
PCI interface. Programming of ICP DMA is described in
Section 14.6, “Operation and Programming.”
HE (Host enable). This bit is initialized to ’0’, which pre-
vents the DSPCPU from serving as the host CPU in the
PCI system. If this bit is set to one, the Enable Mastering
(EM) bit in the PCI Configuration register (see
11.5.3, “Command
PNX1300 must be enabled to serve as a PCI bus initiator
to perform PCI configuration).
CR (PCI clear reset). This bit releases the DSPCPU
from its reset state. The PNX1300 device driver (execut-
ing on an external host CPU) sets this bit to ’1’ after it
completes PNX1300’s configuration. The DSPCPU
starts to execute the pointed by DRAM_BASE MMIO
register.
SR (PCI set reset). This bit forces the DSPCPU into its
reset state. Writing ’1’ to this bit resets the CPU; writing
’0’ causes no action. The PNX1300 device driver (exe-
cuting on an external host CPU) can set this bit to reset
the DSPCPU. This form of reset resets only CPU and In-
struction cache. The Dcache is NOT reset, nor are any
peripherals.
RMD (Read Multiple Disable). In default operating
mode, the RMD bit should be set to ‘0’. In that case, the
BIU uses ‘memory read multiple’ PCI transactions for
BIU DMA, and ‘memory read’ PCI transactions for
DSPCPU reads to PCI space. If the RMD bit is set, DMA
transactions are forced to also use the - less efficient -
memory read transactions. Note that TM-1000 only used
memory read transactions.
11.6.6
The 30-bit PCI_ADR register is intended to be written
only by the data cache. PCI_ADR participates in the spe-
cial two-cycle data-cache-to-PCI protocol. See
11.6.7, “PCI_DATA Register,”
Only the DSPCPU can write to PCI_ADR. External PCI
initiators can neither read nor write this register.
DSPCPU software should not write to this register (by
writing to PCI_ADR in MMIO space). This register is in-
tended only to support the special protocol between the
11-12
BIU_CTL Bit
2
3
4
5
6
7
PCI_ADR Register
config_cycle done
io_cycle done
dma_cycle done
pci_dram write cycle done
second config_cycle or io_cycle requested
second dma_cycle requested
If set to ‘1’, interrupt DSPCPU when...
Register”) is also set to ’1’ (since
PRELIMINARY SPECIFICATION
for more information.
Section
Section
data cache and PCI bus. An unexpected write to
PCI_ADR via MMIO space will not be prevented by hard-
ware and may result in data corruption on the PCI bus.
11.6.7
The 32-bit PCI_DATA register is intended to be used
only by the data cache. PCI_DATA participates in the
special two-cycle data-cache-to-PCI protocol.
The PCI_DATA and PCI_ADR registers are used togeth-
er by the data cache to perform a single data phase PCI
memory-space read or write. A read operation is trig-
gered when the data cache has written the transaction
address into PCI_ADR and asserted the internal signal
pci_read_operation (a direct internal connection be-
tween the data cache and PCI interface). A write opera-
tion is triggered when the data cache has written both
PCI_ADR
pci_read_operation deasserted.
While the PCI interface is performing the PCI read or
write, the DSPCPU is stalled waiting for the completion
of the PCI transaction. When the PCI transaction is com-
plete, the PCI interface asserts pci_ready (a direct inter-
nal connection between the data cache and PCI inter-
face). To finish a read operation, the data cache reads
the PCI_DATA register, forwards the data to the
DSPCPU, and then unlocks the DSPCPU. To finish a
write, the data cache simply unlocks the DSPCPU.
Note that, if the DSPCPU attempts to access a non-exis-
tent PCI address, an RMA condition occurs. In this case,
the value in the PCI_DATA register is set to ‘0’. Hence,
the DSPCPU always reads non-existent PCI locations as
‘0’.
Normal MMIO write operations to PCI_DATA have no ef-
fect. Reads return the register’s current value. External
PCI initiators can neither read nor write this register.
11.6.8
The CONFIG_ADR register is written by the DSPCPU to
set up for a configuration cycle. When PNX1300 is acting
as the host CPU, it must configure devices on the PCI
bus. The DSPCPU writes CONFIG_ADR to select a con-
figuration register within a specific PCI device. See
tion 11.6.10, “CONFIG_CTL Register,”
mation on initiating configuration cycles.
Following are descriptions of the fields of CONFIG_ADR.
BN (PCI bus number). The BN field (the two least-sig-
nificant bits of CONFIG_ADR) selects one of four possi-
ble PCI buses. A value of ’0’ for BN means that the tar-
geted device is on the PCI bus directly connected to
PNX1300 and that any PCI-to-PCI bridges should ignore
the configuration address. Any value for BN other than ’0’
means that the targeted device is on a PCI bus connect-
ed to a PCI-to-PCI bridge and that all devices directly
connected to PNX1300’s local PCI bus should ignore the
configuration address.
RN (Register number). The RN field (bits 2..7 of
CONFIG_ADR) is used to specify one of the 64 configu-
PCI_DATA Register
CONFIG_ADR Register
and
PCI_DATA
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