PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 65

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
The instruction scheduler uses interruptible jumps exclu-
sively for inter-decision tree jumps. Hence, within a deci-
sion tree, no special-event processing can be initiated. If
a tree-to-tree jump is taken, special-event processing is
allowed. Since the only registers live at this point (i.e.,
that contain useful data) are the global registers allocat-
ed by the ANSI C compiler, only a subset of the registers
needs to be preserved by the event handlers. Refer to
the TriMedia SDE Reference Manual for details on which
registers can be in use. The DSPCPU register state can
be described by the contents of this subset of general
purpose registers and the contents of the PCSW and the
DPC value (the target of the inter-tree jump).
The priority resolution mechanism built into the DSPCPU
hardware dispatches the highest-priority, non-masked
special-event request at the time of a successful inter-
ruptible jump operation. In view of the simple, real-time-
oriented nature of the mechanisms provided, only limited
nesting of events should be allowed.
3.5.1
RESET is the highest priority special event. It is asserted
by external hardware or by the host CPU. PNX1300 will
respond to it at any time.
External hardware reset through the TRI_RESET# pin
initiates boot protocol execution as described in
13, “System Boot.”
be lost and instruction execution to start from address
DRAM_BASE.
A PCI host CPU can perform a PNX1300 DSPCPU-only
reset by an MMIO write to the BIU_CTL.SR and CR bits.
Such a reset does not cause a full boot, instead the
DSPCPU resumes execution from DRAM_BASE.
3.5.2
The DSPCPU enters EXC special-event processing un-
der the following conditions:
1. RESET is de-asserted.
2. The intersection PCSW[15,6:0] & PCSW[31,22:16] is
3. A successful interruptible jump is in the final jump ex-
DSPCPU hardware takes the following actions on the ini-
tiation of EXC processing:
Figure 3-6. Interrupt vector locations in MMIO address space.
non-empty or PCSW.TFE is set.
ecution stage.
MMIO_BASE
0x10 08FC
0x10 08F8
0x10 0888
0x10 0884
0x10 0880
offset:
RESET
EXC (Exceptions)
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This causes the current PC value to
INTVEC31 (r/w)
INTVEC30 (r/w)
INTVEC2 (r/w)
INTVEC1 (r/w)
INTVEC0 (r/w)
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31
Chapter
1. DPC is assigned the intended destination address of
2. Instruction processing starts at EXCVEC.
All other actions are the responsibility of the EXC handler
software. Note that no other special event processing will
take place until the handler decides to execute an inter-
ruptible jump that succeeds.
3.5.3
The on-chip Vectored Interrupt Controller (VIC) provides
32 INT request input hardware lines. The interrupt con-
troller prioritizes and maps attention requests from sev-
eral different peripherals onto successive INT requests
to the DSPCPU.
INT special event processing will occur under the follow-
ing conditions:
1. RESET is de-asserted.
2. The intersection PCSW[15,6:0] & PCSW[31,22:16] is
3. The intersection of IPENDING and IMASK is non-
4. The interrupt is at level NMI or PCSW.IEN = 1.
5. A successful interruptible jump is in the final jump ex-
DSPCPU hardware takes the following actions on the ini-
tiation of NMI or INT processing:
1. DPC gets assigned the intended destination address
2. Instruction processing starts at the appropriate inter-
All other actions are the responsibility of the INT handler
software. Note that no other special event processing will
take place until the handler decides to execute an inter-
ruptible jump that succeeds.
3.5.3.1
Each of the 32 interrupt sources can be assigned an ar-
bitrary interrupt vector (the address of the first instruction
of the interrupt handler). A vector is setup by writing the
address to one of the MMIO locations shown in
Figure
defined after RESET. (Addresses of the MMIO vector
registers are offset with respect to MMIO_BASE.)
PRELIMINARY SPECIFICATION
the successful jump.
empty and PCSW.TFE is not set.
empty.
ecution stage.
of the successful jump.
rupt vector.
Source 31 vector
Source 30 vector
Source 2 vector
Source 1 vector
Source 0 vector
3-6. The state of the MMIO vector locations is un-
INT and NMI (Maskable and Non-
Maskable Interrupts)
Interrupt vectors
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DSPCPU Architecture
0
3-9