PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 375

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
iavgonep
SYNTAX
FUNCTION
DESCRIPTION
sum rsrc1+rsrc2+1, shifts the sum right by 1 bit, and stores the result into rdest. The operands are signed integers.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-77
r60 = 0x10, r70 = 0x20
r10 = 0, r60 = 0x10, r30 = 0x20
r20 = 1, r60 = 0x9, r30 = 0x20
r70 = 0xfffffff7, r40 = 0x2
r70 = 0xfffffff7, r40 = 0x3
As shown below, the
The
[ IF rguard ] iavgonep rsrc1 rsrc2 → rdest
if rguard then
rsrc1
rdest ← (sign_ext32to64(rsrc1) + sign_ext32to64(rsrc2) + 1) >> 1;
iavgonep
31
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
iavgonep
PRELIMINARY SPECIFICATION
Full precision
33-bit result
signed
rdest
32
operation returns the average of the two arguments. This operation computes the
S
31
iavgonep r60 r70 → r80
IF r10 iavgonep r60 r30 → r50
IF r20 iavgonep r60 r30 → r90
iavgonep r70 r40 → r100
iavgonep r70 r40 → r100
S
0
Operation
signed
signed
+
shift down one bit
rsrc2
1
31
0
0
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r80 ← 0x18
no change, since guard is false
r90 ← 0x15
r100 ← 0xfffffffd
r100 ← 0xfffffffd
signed
Philips Semiconductors
quadavg iadd
Signed average
ATTRIBUTES
SEE ALSO
Result
dspalu
1, 3
No
25
—
0
2
2