PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 179

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
PNX1300 generates memory write-and-invalidate PCI
transactions if all conditions below are satisfied, other-
wise it generates regular memory write transactions:
• The MWI bit in the Command Register is set.
• The Cache Line Size register is set to 4,8, or 16 32-
• The DMA source address is 64 byte aligned.
• The DMA destination address is cache line size
• The T bit is set
PNX1300 generates ‘memory read multiple’ PCI transac-
tions for DMA reads, unless the RMD (Read Multiple Dis-
able) bit is set in BIU_CTL, in which case the less effi-
cient ‘memory read’ transactions are used.
During a PCI → SDRAM block transfer, the PCI interface
drives the PCI bus with the address from SRC_ADR. The
returned data is buffered in r_buffer. The PCI interface
then drives the address from DEST_ADR and the data
from r_buffer to the SDRAM controller. SRC_ADR and
DEST_ADR are incremented, the TL field in DMA_CTL
is decremented, and this sequence repeats until TL
reaches ‘0’.
At the end of the PCI → SDRAM block transfer, the PCI
interface will generate a DSPCPU interrupt if the appro-
priate IntE bit is set in BIU_CTL. Alternatively, DSPCPU
software can poll the appropriate ‘done’ status bit in
BIU_STATUS.
During an SDRAM → PCI block transfer, the PCI inter-
face drives the address from SRC_ADR to the SDRAM
controller. The returned data is buffered in w_buffer. The
PCI interface then drives the address from DEST_ADR
and the data from w_buffer to the PCI bus. SRC_ADR
and DEST_ADR are incremented, the TL field in
DMA_CTL is decremented, and this sequence repeats
until TL reaches ‘0’.
At the end of the SDRAM → PCI block transfer, the PCI
interface can generate a DSPCPU interrupt if the appro-
priate IntE bit is set in BIU_CTL. Alternatively, DSPCPU
software can poll the appropriate ‘done’ status bit in
BIU_STATUS.
11.6.17 INT_CTL Register
The INT_CTL register contains three fields for setting,
enabling, and sensing the four PCI interrupt lines.
Table 11-19
INT_CTL.
INT (Interrupt bits). The INT field (bits 0..3 of INT_CTL)
can force a PCI interrupt to be signalled.
IE (Interrupt enable). The IE field (bits 4..7 of INT_CTL)
enables PNX1300 to drive PCI interrupt lines.
IS (Interrupt state). The IS field (bits 8..11 of INT_CTL)
senses the state of the PCI interrupt lines.
Figure 11-9
used to implement the control of each intx# pin.
See also
bit words.
aligned.
Section 3.6, “PNX1300 to Host Interrupts.”
shows a conceptual realization of the logic
shows the interpretation of the fields in
Figure 11-9. Conceptual realization of intx# pin con-
trol logic.
Table 11-19. INT_CTL Bits
11.7
PNX1300’s PCI interface can generate and respond to
several types of PCI bus commands.
the 12 possible commands and whether or not PNX1300
can generate them.
Table 11-20. PNX1300 PCI Commands as Initiator
Table 11-21
er or not PNX1300 can respond to them.
The basic transfer mechanism on the PCI bus is a burst,
which consists of an address phase followed by one or
more data phases. In PNX1300, the DSPCPU and ICP
are the only two units that can cause PNX1300 to be-
PRELIMINARY SPECIFICATION
Configuration read
Configuration write
Memory read
Memory read multiple
Memory write
Memory write and invalidate
I/O read
I/O write
Field
INT
INT_CTL
IE
IS
INTx
IEx
ISx
PNX1300 Generates
PCI BUS PROTOCOL OVERVIEW
Bit
10
11
0
1
2
3
4
5
6
7
8
9
lists the 12 possible commands and wheth-
PCI Signal
inta#
intb#
intc#
intd#
inta#
intb#
intc#
intd#
inta#
intb#
intc#
intd#
oc
0 ⇒ Deassert intx#
1 ⇒ Assert intx# (if enabled);
0 ⇒ Disable open-collector
1 ⇒ Enable open-collector
Reads state of intx# pin:
0 ⇒ No interrupt asserted
1 ⇒ Interrupt is asserted
Interrupt acknowledge
Special cycle
Dual address
Memory read line
i.e., pull intx# pin to a low
logic level
output to intx#
output to intx#
(intx# is high)
(intx# is low)
Programming
PNX1300 Cannot
Table 11-20
Generate
PCI Interface
PCI intx#
11-15
lists