PIC24FV16KA301-I/P Microchip Technology, PIC24FV16KA301-I/P Datasheet - Page 167
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PIC24FV16KA301-I/P
Manufacturer Part Number
PIC24FV16KA301-I/P
Description
MCU 16KB FLASH 2KB RAM 20-PDIP
Manufacturer
Microchip Technology
Datasheet
1.PIC24FV16KA301-IP.pdf
(320 pages)
Specifications of PIC24FV16KA301-I/P
Controller Family/series
PIC24F
Core Size
16bit
No. Of I/o's
17
Program Memory Size
16KB
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
32MHz
Oscillator Type
External, Internal
Rohs Compliant
Yes
Processor Series
PIC24FV
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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To set up the SPI1 module for the Enhanced Buffer
Master (EBM) mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 16-2:
2011 Microchip Technology Inc.
SS1/FSYNC1
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
Clear the SPIROV bit (SPI1STAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
SDO1
SCK1
SDI1
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register.
Read SPI1BUF
Control
Transfer
Sync
SPIx MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
Receive Buffer
8-Level FIFO
bit 0
Control
SPI1SR
Clock
SPI1BUF
Shift Control
Transmit Buffer
8-Level FIFO
PIC24FV32KA304 FAMILY
Transfer
Write SPI1BUF
Select
Edge
To set up the SPI1 module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPI1BUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.
Clear the SPIROV bit (SPI1STAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Secondary
1:1 to 1:8
Prescaler
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
Internal Data Bus
1:1/4/16/64
Prescaler
Primary
DS39995B-page 167
SPI1CON1<1:0>
SPI1CON1<4:2>
Enable
Master Clock
F
CY
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