PIC24FV16KA301-I/P Microchip Technology, PIC24FV16KA301-I/P Datasheet - Page 216

• Manufacturer Part Number: PIC24FV16KA301-I/P
• Description: MCU 16KB FLASH 2KB RAM 20-PDIP
• Manufacturer: Microchip Technology

Specifications of PIC24FV16KA301-I/P

• Controller Family/series: PIC24F
• Core Size: 16bit
• No. Of I/o's: 17
• Program Memory Size: 16KB
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 2KB
• Cpu Speed: 32MHz
• Oscillator Type: External, Internal
• Rohs Compliant: Yes
• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FV32KA304 FAMILY
REGISTER 22-2:
DS39995B-page 216
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-2
bit 1
bit 0
Note 1:
PVCFG1
BUFS
R/W-0
R/W-0
(1)
Only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only used
when BUFM = 1.
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
11 = Internal VRH2
10 = Internal VRH1
01 = External V
00 = AV
NVCFG0: Converter Negative Voltage Reference Configuration bits
1 = External V
0 = AV
OFFCAL: Offset Calibration Mode Select bit
1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AV
0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ During SAMPLE A bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
1 = A/D is filling the upper half of the buffer; user should access data in the lower half
0 = A/D is filling the lower half of the buffer; user should access data in the upper half
SMPI<4:0>: Interrupt Sample Rate Select bits
11111 = Interrupts at the completion of conversion for each 32nd sample
11110 = Interrupts at the completion of conversion for each 31st sample



00001 = Interrupts at the completion of conversion for every other sample
00000 = Interrupts at the completion of conversion for each sample
BUFM: Buffer Fill Mode Select bit
1 = Starts buffer filling at AD1BUF0 on first interrupt and AD1BUF(n/2) on next interrupt
0 = Starts filling buffer at address, ADCBUF0, and each sequential address on successive interrupts
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample
0 = Always uses channel input selects for SAMPLE A
PVCFG0
SMPI4
R/W-0
R/W-0
(Split Buffer mode)
(FIFO mode)
AD1CON2: A/D CONTROL REGISTER 2
SS
DD
W = Writable bit
‘1’ = Bit is set
REF
REF
NVCFG0
SMPI3
R/W-0
R/W-0
-
+
(1)
OFFCAL
SMPI2
R/W-0
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BUFREGEN
SMPI1
R/W-0
R/W-0
CSCNA
SMPI0
R/W-0
R/W-0
 2011 Microchip Technology Inc.
x = Bit is unknown
BUFM
R/W-0
U-0
—
(1)
SS
R/W-0
ALTS
U-0
—
bit 8
bit 0