AD9548BCPZ Analog Devices Inc, AD9548BCPZ Datasheet - Page 108

IC CLOCK GEN/SYNCHRONIZR 88LFCSP

AD9548BCPZ

Manufacturer Part Number
AD9548BCPZ
Description
IC CLOCK GEN/SYNCHRONIZR 88LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9548BCPZ

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
88-LFCSP
Frequency-max
*
Clock Ic Type
Clock Synthesizer
Ic Interface Type
Serial
Frequency
1GHz
No. Of Outputs
4
No. Of Multipliers / Dividers
4
Supply Current
190mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9548BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9548BCPZ-SMD7
Manufacturer:
SHARP
Quantity:
392
AD9548
If x is an integer, then y = x. Otherwise, y is the nearest integer to
x. For example, round(2.1) = 2, round(2.5) = 3, and round(−3.1) =
−3.
The ceil() function
If x is an integer, then y = x. Otherwise, y is the next integer to
the right on the number line. For example, ceil(2.8) = 3,
whereas ceil(−2.8) = −2.
The min() function
where x
is the number in the list that is the farthest to the left on the
number line.
The max() function
where x
is the number in the list that is the farthest to the right on the
number line.
The log
where ln() is the natural log function and x is a positive,
nonzero number.
Assume that the coefficient calculations for , , , and yield
the following results:
These values are floating point numbers that must be quantized
according to the bit widths of the linear and exponential
components of the coefficients as they appear in the register
map. Note that the calculations that follow indicate a positive
value for the register entries of and . The reason is that and
AD9548 registers as positive values. The AD9548 converts the
stored values to negative numbers within its signal processing
core. A detailed description of the register value computations
for , ,
Register Values section to the Calculation of the Register
Values section.
CALCULATION OF THE REGISTER VALUES
The quantized
, which are supposed to be negative values, are stored in the
2
, and
y = ceil(x)
y = min(x
y = max(x
log
2
0
0
() function
2
through x
through x
. 0
3
(
. 0
. 7
x
according to
. 6
and is contained in the Calculation of the
002015399
012735446
)
50373
quantized
98672
0
0
, x
ln
ln
, x
coefficient consists of four components,
(
(
1
1
, ... x
) 2
x
, ... x
n
n
)
10
is a list of real numbers, and the value of y
is a list of real numbers, and the value of y
10
n
n
5
)
5
)
0
2
16
1
2
3
0
Rev. A | Page 108 of 112
,
1
,
where
front-end gain and
binary decimal point of
values of . Calculation of
If gain is necessary (that is,
most or all of it to the front-end gain (
calculation of
three-step process that leads directly to the calculation of
Calculation of
Using the example value of
This leads to the following quantized value, which is very close
to the desired value of 0.012735446:
CALCULATION OF THE REGISTER VALUES
The quantized coefficient consists of two components,
where
two-step process that leads to the calculation of
a two-step process.
Using the example value of − = 6.98672 × 10
1
according to
w = 6, so
x = 0 and y = 0, so
z = 53,416.332099584, so
x = 13, so
y = 75,019.3347657728, so
w
x
z
x
y
y
1
2
3
quantized
1
0
0
0
0
,
and
if
if
if
round
round
if
if
ceil
if
min
min
1
(
(
min
(
,
(
(
(
quantized
y
y
2
1
(log
2
, and
0
are the register values. Calculation of
31
131
is to be done before
, 1
(
(
, 1
= 6
65
, 1
is a two-step process, as follows:
53416
= 13
, 1
, 8
, 8
,
ceil
min
,
2
max(
3
min
535
,
, 7
(
071
ceil
provides back-end gain, and
y
3
2
(log
2
are the register values.
y
16
22
17
))
0
)
,
63
(log
2
, 7
= 0 and
0
to the left to accommodate small
, 0
,
max(
,
2
1
1
max(
,
22
max(
) 0
(
1
is a two-step process, as follows:
= 0.012735446 yields
> 1), then it is beneficial to apply
x
max(
2
)
2
)
2
(
)),
(
, 1
= 53,416
17
. 0
, 1
= 75,019
3
, 0
)),
) 0
, 0
0127356682
)
z
y
x
)
= 0
1
) 0
w
)
3
)
, )
. Calculation of
2
, )
) implying that the
) 0
) 0
−5
yields
2
1
0
provides
, which is also
1
shifts the
1
is a
2
is a
0
3
and
.

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