AD9548BCPZ Analog Devices Inc, AD9548BCPZ Datasheet - Page 9

• Manufacturer Part Number: AD9548BCPZ
• Description: IC CLOCK GEN/SYNCHRONIZR 88LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9548BCPZ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 88-LFCSP
• Frequency-max: *
• Clock Ic Type: Clock Synthesizer
• Ic Interface Type: Serial
• Frequency: 1GHz
• No. Of Outputs: 4
• No. Of Multipliers / Dividers: 4
• Supply Current: 190mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
OUTPUT TIMING SKEW
ZERO-DELAY TIMING SKEW
1
DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN)
Table 12.
Parameter
DAC OUTPUT CHARACTERISTICS
(DACOUTP/DACOUTN)
The listed values are for the slower edge (rise or fall).
Rise/Fall Time
Duty Cycle
Output Voltage High (V
Output Voltage Low (V
Between LVPECL Outputs
Between LVDS Outputs
Between CMOS 3.3 V Outputs
Between CMOS 1.8 V Outputs
Between LVPECL Outputs and LVDS
Between LVPECL Outputs and CMOS
Frequency Range
Output Offset Voltage
Voltage Compliance Range
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
3.3 V Supply
1.8 V Supply
AVDD3 = 3.3 V, I
AVDD3 = 3.3 V, I
AVDD3 = 1.8 V, I
AVDD3 = 3.3 V, I
AVDD3 = 3.3 V, I
AVDD3 = 1.8 V, I
Strong Drive Strength Setting
Weak Drive Strength Setting
Outputs
Outputs
Strong Drive Strength Setting
Weak Drive Strength Setting
1
(20% to 80%)
OH
OH
OH
OL
OL
OL
= 10 mA
= 1 mA
= 1 mA
= 10 mA
= 1 mA
= 1 mA
OL
OH
)
)
Min
40
2.6
2.9
1.5
Min
62.5
VSS − 0.5
−12
Typ
0.5
8
1.5
14
13
23
24
40
14
19
±5
Rev. A | Page 9 of 112
Typ
0.5
50
5
20
125
Max
2
14.5
2.5
60
0.3
0.1
0.1
138
240
140
Max
450
15
VSS + 0.5
+12
Unit
ns
ns
ns
%
V
V
V
V
V
V
ps
ps
ps
ps
ps
ps
ps
ns
Unit
MHz
mV
V
Ω
pF
mA
% FS
Test Conditions/Comments
10 pF load
10 pF load
Output driver static; strong drive strength
setting
Output driver static; strong drive strength
setting
10 pF load
Rising edge only; any divide value
Rising edge only; any divide value
Weak drive not supported at 1.8 V
Output relative to active input reference;
output distribution synchronization to
active reference feature enabled; assumes
manual phase offset compensation of
deterministic latency
Test Conditions/Comments
This is the single-ended voltage at
either DAC output pin (no external
load) when the internal DAC code
implies that no current is delivered
to that pin.
Single-ended, each pin has an
internal 50 Ω termination to VSS.
Programmable (8 mA to 31 mA; see
the DAC Output section).
AD9548