AD9548BCPZ Analog Devices Inc, AD9548BCPZ Datasheet - Page 98

• Manufacturer Part Number: AD9548BCPZ
• Description: IC CLOCK GEN/SYNCHRONIZR 88LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9548BCPZ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 88-LFCSP
• Frequency-max: *
• Clock Ic Type: Clock Synthesizer
• Ic Interface Type: Serial
• Frequency: 1GHz
• No. Of Outputs: 4
• No. Of Multipliers / Dividers: 4
• Supply Current: 190mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9548
Register 0D02 to Register 0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0209 to Address 0210), then the appropriate IRQ monitor bit is set to a Logic 1 when
the indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0A04 to Address 0A0B), the reset all
IRQs bit (Register 0A03, Bit 1), or a device reset.
Table 132. IRQ Monitor for SYSCLK
Address
0D02
Table 133. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address
0D03
Table 134. IRQ Monitor for the Digital PLL
Address
0D04
Table 135. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit
Address
0D05
Table 136. IRQ Monitor for Reference Inputs
Address
0D06
Bits
[7:6]
[5]
[4]
[3:2]
[1]
[0]
Bits
[7:4]
[3]
[2]
[1]
[0]
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
[7:5]
[4]
[3]
[2]
[1]
[0]
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Switching
Closed
Freerun
Holdover
Freq unlocked
Freq locked
Phase unlocked
Phase locked
Ref AA new profile
Ref AA validated
Ref AA fault cleared
Ref AA fault
Ref A fault cleared
Ref A fault
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK Cal complete
SYSCLK Cal started
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Bit Name
Bit Name
Unused
History updated
Freq unclamped
Freq clamped
Phase slew unlimited
Phase slew limited
Bit Name
Ref A new profile
Ref A validated
Indicates that the DPLL is switching to a new reference
Indicates that the DPLL has entered closed-loop operation
Indicates that the DPLL has entered free-run mode
Indicates that the DPLL has entered holdover mode
Indicates that the DPLL lost frequency lock
Indicates that the DPLL has acquired frequency lock
Indicates that the DPLL lost phase lock
Indicates that the DPLL has acquired phase lock
Description
Indicates that Ref AA has switched to a new profile
Indicates that Ref AA has been validated
Indicates that Ref AA has been cleared of a previous fault
Indicates that Ref AA has been faulted
Indicates that Ref A has switched to a new profile
Indicates that Ref A has been validated
Indicates that Ref A has been cleared of a previous fault
Indicates that Ref A has been faulted
Description
Indicates a SYSCLK PLL state transition from locked to unlocked
Indicates a SYSCLK PLL state transition from unlocked to locked
Indicates that SYSCLK calibration has completed
Indicates that SYSCLK calibration has begun
Description
Description
Indicates a distribution sync event
Indicates expiration of the watchdog timer
Indicates a fault during an EEPROM load or save operation
Indicates successful completion of an EEPROM load or save operation
Description
Indicates the occurrence of a tuning word history update
Indicates a frequency limiter state transition from clamped to unclamped
Indicates a frequency limiter state transition from unclamped to clamped
Indicates a phase slew limiter state transition from slew limiting to not slew
limiting
Indicates a phase slew limiter state transition from not slew limiting to slew
limiting
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