MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 26

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

sequence. SCLK can idle either high or low between tran-
sitions. Figure 7 shows the detailed timing diagram of the
3-wire serial interface.
Figure 8 shows the mode-recovery timing diagram.
t
or standby mode and entering Rx, Tx, or FD mode.
t
either Rx or Tx mode. t
the Rx ADC to settle within 1dB of specified SINAD per-
formance and Tx DAC settling to 10 LSB error. t
and t
serial command is latched into the MAX19711 by a
CS/WAKE transition high. In FAST mode, the recovery
time is 0.1µs to switch to Rx mode and 1µs to switch to
Tx mode.
Both the Rx ADC and Tx DAC share the CLK input. The
CLK input accepts a CMOS-compatible signal level set
by OV
sion of the device depends on the repeatability of the
rising and falling edges of the external clock, use a
clock with low jitter and fast rise and fall times (< 2ns).
Specifically, sampling occurs on the rising edge of the
clock signal, requiring this edge to provide the lowest
possible jitter. Any significant clock jitter limits the SNR
performance of the on-chip Rx ADC as follows:
where f
t
Clock jitter is especially critical for undersampling appli-
cations. Consider the clock input as an analog input
10-Bit, 11Msps, Full-Duplex
Analog Front-End
26
WAKE
ENABLE
AJ
Figure 8. Mode-Recovery Timing Diagram
is the time of the clock jitter.
______________________________________________________________________________________
ENABLE
CS/WAKE
DD
is the wake-up time when exiting shutdown, idle,
IN
SCLK
DIN
is the recovery time when switching between
from 1.8V to V
SNR
AD0–AD9
represents the analog input frequency and
ID/QD
times are measured after either the 16-bit
=
20
×
log
System Clock Input (CLK)
WAKE
DD
⎛
⎜
⎝
2
Mode-Recovery Timing
. Since the interstage conver-
×
or t
π
×
ENABLE
1
f
IN
×
t
AJ
is the time for
⎞
⎟
⎠
WAKE
and route away from any analog input or other digital
signal lines. The MAX19711 clock input operates with
an OV
±15% duty cycle.
When the clock signal is stopped at CLK input (CLK =
0V or OV
and the MAX19711 saves the last power-management
mode or Tx/Rx/FD command. All converter circuits (Rx
ADC, Tx DAC, aux-ADC, and aux-DACs) hold their last
value. When the clock signal is restarted at CLK, allow
7.2µs (clock wake-up time) for the internal clock circuit-
ry to settle before updating the Tx DAC, reading a valid
Rx ADC conversion result, or starting an aux-ADC con-
version. This ensures the converters (Rx ADC, Tx DAC,
aux-ADC) meet all dynamic performance specifications.
The aux-DAC channels are not dependent on CLK, so
they may be updated when CLK is idle.
The MAX19711 includes three 12-bit aux-DACs (DAC1,
DAC2, DAC3) with 1µs settling time for controlling vari-
able-gain amplifier (VGA), automatic gain-control
(AGC), and automatic frequency-control (AFC) func-
tions. The aux-DAC output range is 0.2V to 2.57V as
defined by V
AGC outputs (DAC2 and DAC3) are at zero. The AFC
DAC (DAC1) is at 1.1V during power-up. The aux-DACs
can be independently controlled through the SPI bus,
except during SHDN mode where the aux-DACs are
turned off completely and the output voltage is set to
zero. In STBY and IDLE modes the aux-DACs maintain
the last value. On wake-up from SHDN, the aux-DACs
resume the last values.
Loading on the aux-DAC outputs should be carefully
observed to achieve specified settling time and stabili-
ty. The capacitive load must be kept to a maximum of
5pF including package and trace capacitance. The
DD
DD
/ 2 voltage threshold and accepts a 50%
), all internal registers hold their last value
OH
16-BIT SERIAL DATA INPUT
- V
12-Bit, Auxiliary Control DACs
OL
. During power-up, the VGA and
ADC DIGITAL OUTPUT SINAD
SETTLES TO WITHIN 1dB
t
DAC ANALOG OUTPUT
SETTLES TO 10 LSB ERROR
t
WAKE,SD,ST_
WAKE,SD,ST_
TO Rx MODE OR t
TO Tx MODE OR t
ENABLE
ENABLE
,
,
TX
RX