MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 9

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, V
DAC output, C
values are at T
Note 1: Specifications from T
Note 2: The minimum clock frequency (f
Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
Note 5: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output
Note 6: Guaranteed by design and characterization.
BUFFERED EXTERNAL REFERENCE (external V
Reference Input Voltage
Differential Reference Output
Common-Mode Output Voltage
Maximum REFP/REFN/COM
Source Current
Maximum REFP/REFN/COM
Sink Current
REFIN Input Current
REFIN Input Resistance
DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0)
Input High Threshold
Input Low Threshold
Input Leakage
Input Capacitance
DIGITAL OUTPUTS (AD9–AD0, DOUT)
Output-Voltage Low
Output-Voltage High
Tri-State Leakage Current
Tri-State Output Capacitance
DD
= 3V, OV
zation.
(A
15.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con-
version time (for no averaging, NAVG = 1) will be t
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tones.
signals using a sine-wave fit.
CLK
PARAMETER
A
REFP
DD
) is determined by f
= +25°C.) (Note 1)
= 1.8V, internal reference (1.024V), C
= C
_______________________________________________________________________________________
REFN
= C
A
= +25°C to +85°C guaranteed by production test. T
COM
CLK
= 0.33µF, C
and the chosen aux-ADC clock-divider value. The minimum aux-ADC A
SYMBOL
I
SOURCE
V
V
CLK
V
I
C
I
DC
V
V
REFIN
DI
V
LEAK
SINK
V
COM
DIFF
OUT
INH
INL
OH
OL
IN
IN
) for the MAX19711 is 2MHz (typ). The minimum aux-ADC sample rate clock frequency
L
< 5pF on all aux-DAC outputs, T
V
CLK, SCLK, DIN, CS/WAKE = OGND or
OV
DA9–DA0 = OV
DA9–DA0 = OGND
I
I
REFIN
SINK
SOURCE
REFP
DD
L
≈ 10pF on all digital outputs, f
= 200µA
10-Bit, 11Msps, Full-Duplex
- V
= 1.024V applied; V
CONV
FS
= 200µA
REFN
= 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx
(max) = (12 x 1 x 128) / 2MHz = 768µs.
CONDITIONS
DD
REFP
A
A
, V
Analog Front-End
< +25°C guaranteed by design and characteri-
= T
REFN
CLK
MIN
= 11MHz (50% duty cycle), Rx ADC input
, V
to T
COM
0.7 x OV
0.8 x OV
MAX
MIN
-1
-1
-5
-1
levels are generated internally)
, unless otherwise noted. Typical
DD
DD
V
1.024
0.512
DD
TYP
-0.7
500
2
2
5
5
CLK
/ 2
0.3 x OV
0.2 x OV
> 2MHz / 128 =
MAX
+1
+1
+5
+1
DD
DD
UNITS
mA
mA
kΩ
µA
µA
pF
µA
pF
V
V
V
V
V
V
V
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