MAX19711ETN+T Maxim Integrated Products, MAX19711ETN+T Datasheet - Page 27

• Manufacturer Part Number: MAX19711ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19711ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 37.5mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

resistive load must be greater than 200kΩ. If capacitive
loading exceeds 5pF, then add a 10kΩ resistor in
series with the output. Adding the series resistor helps
drive larger load capacitance (< 15pF) at the expense
of slower settling time.
The MAX19711 integrates a 333ksps, 10-bit aux-ADC
with an input 4:1 multiplexer. In the aux-ADC mode reg-
ister, setting bit AD0 begins a conversion with the auxil-
iary ADC. Bit AD0 automatically clears when the
conversion is complete. Setting or clearing AD0 during
a conversion has no effect (see Table 13). Bit AD1
determines the internal reference of the auxiliary ADC
(see Table 14). Bits AD2 and AD3 determine the auxil-
iary ADC input source (see Table 15). Bits AD4, AD5,
and AD6 select the number of averages taken when a
single start-convert command is given. The conversion
time increases as the number of averages increases
(see Table 16). The conversion clock can be divided
down from the system clock by properly setting bits
AD7, AD8, and AD9 (see Table 17). The aux-ADC out-
put data can be written out of DOUT by setting bit
AD10 high (see Table 18).
The aux-ADC features a 4:1 input multiplexer to allow
measurements on four input sources. The input sources
are selected by AD3 and AD2 (see Table 15). Two of
the multiplexer inputs (ADC1 and ADC2) can be con-
nected to external sources such as an RF power detec-
tor like the MAX2208 or temperature sensor like the
MAX6613. The other two multiplexer inputs are internal
Table 13. Auxiliary ADC Convert
Table 15. Auxiliary ADC Input Source
Table 14. Auxiliary ADC Reference
AD3
0
0
1
1
AD0
AD1
0
1
0
1
AD2
0
1
0
1
10-Bit, 333ksps Auxiliary ADC
______________________________________________________________________________________
Internal 2.048V Reference (Default)
Aux-ADC Start-Convert
Internal V
Aux-ADC Idle (Default)
Aux-ADC INPUT SOURCE
SELECTION
SELECTION
ADC1 (Default)
DD
OV
V
ADC2
DD
Reference
DD
/ 2
/ 2
10-Bit, 11Msps, Full-Duplex
connections to V
supply voltages. The internal V
tions are made through integrated dividers that yield
V
ADC voltage reference can be selected between an
internal 2.048V bandgap reference or V
14). The V
measurement of an external voltage source with a full-
scale range extending beyond the 2.048V level. The
input source voltage range cannot extend above V
The conversion requires 12 clock edges (1 for input
sampling, 1 for each of the 10 bits, and 1 at the end for
loading into the serial output register) to complete one
conversion cycle (when no averaging is being done).
Each conversion of an average (when averaging is set
greater than 1) requires 12 clock edges. The conver-
sion clock is generated from the system clock input
(CLK). An SPI-programmable divider divides the sys-
tem clock by the appropriate divisor (set with bits AD7,
AD8, and AD9; see Table 17) and provides the conver-
sion clock to the auxiliary ADC. The auxiliary ADC has a
maximum conversion rate of 333ksps. The maximum
conversion clock frequency is 4MHz (333ksps x 12
clocks). Choose the proper divider value to keep the
conversion clock frequency under 4MHz, based upon
X = Don’t care.
Table 17. Auxiliary ADC Clock (CLK)
Divider
Table 16. Auxiliary ADC Averaging
AD6
DD
AD9
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
/ 2 and OV
AD5
AD8
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
DD
Analog Front-End
AD4
reference selection is provided to allow
AD7
X
0
1
0
1
0
1
DD
0
1
0
1
0
1
0
1
DD
/ 2 measurement results. The aux-
and OV
1 Conversion (No Averaging) (Default)
Aux-ADC CONVERSION CLOCK
Average of 16 Conversions
Average of 32 Conversions
Average of 32 Conversions
CLK Divided by 1 (Default)
Average of 2 Conversions
Average of 4 Conversions
Average of 8 Conversions
Aux-ADC AVERAGING
DD
CLK Divided by 128
CLK Divided by 16
CLK Divided by 32
CLK Divided by 64
CLK Divided by 2
CLK Divided by 4
CLK Divided by 8
that monitor the power-
DD
and OV
DD
DD
(see Table
connec-
DD
27
.