ISL95311UIU10Z-TK Intersil, ISL95311UIU10Z-TK Datasheet - Page 7

• Manufacturer Part Number: ISL95311UIU10Z-TK
• Description: IC XDCP 128-TAP 50KOHM 10-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL95311UIU10Z-TK

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On applying power to the ISL95311, the V
have a monotonic ramp to the specified operating voltage. It
is important that once V
least 2.5V in less than 7.5ms (0.2V/ms). The ramp rate
before and after these thresholds is not important.
V
Under no condition should V+ be applied without V
the sequence of applying V+ and V
not affect the proper recall of the wiper position, applying V+
before V
before the electronic switch control signals are applied. This
can result in multiple electronic switches being turned on,
which could load the power supply and cause brief,
unexpected potentiometer wiper settings.
To prevent unknown wiper positions on the ISL95311 on
power-down, it is recommended that V+ turn off before or
simultaneously with V
off, the wiper position can remain unchanged from its
previous setting or it can go to an undefined state.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by a 7-bit volatile Wiper
Register (WR). When the WR contains all zeroes (00h), the
wiper terminal (R
When the WR contains all ones (7Fh), the wiper terminal
(R
WR increases from all zeroes (00h) to all ones (7Fh), the
wiper moves monotonically from the position closest to R
the position closest to R
between R
resistance between R
While the ISL95311 is being powered up, the WR is reset to
20h (64 decimal), which locates the R
R
large enough for reliable non-volatile memory reading, the
ISL95311 reads the value stored on a non-volatile Initial Value
Register (IVR) and loads it into the WR.
The WR and IVR can be read from or written to directly using
the I
sections.
Memory Description
The ISL95311 contains 1 non-volatile byte know as the Initial
Value Register (IVR). It is accessed by the I
operations with Address 00h. The IVR contains the value
which is loaded into the Volatile Wiper Register (WR) at
power-up.
CC
L
W
and R
) is closest to its “High” terminal (R
2
must be applied prior to, or simultaneously, with V+.
C serial interface as described in the following
CC
H
. Soon after the power supply voltage becomes
W
powers the electronic switches of the DCP
and R
H
W
and R
) is closest to its “Low” terminal (R
L
increases monotonically, while the
CC
H
CC
and R
H
. If V+ remains on after V
L
. At the same time, the resistance
pins). The R
reaches 1V that it increases to at
W
7
decreases monotonically.
CC
W
H
to the ISL95311 does
W
at the center between
). As the value of the
pin is connected to
CC
2
C interface
supply should
CC
CC
. While
L
turns
).
L
to
ISL95311
The volatile WR, and the non-volatile IVR of a DCP are
accessed with the same address.
The Access Control Register (ACR) determines which word
at address 00h is accessed (IVR or WR). The volatile ACR
must be set as follows:
When the ACR is all zeroes, which is the default at power-up:
• A read operation to address 0 outputs the value of the
• A write operation to address 0 writes the identical values
• When the ACR is 80h:
• A read operation to address 0 outputs the value of the
• A write operation to address 0 only writes to the
It is not possible to write to an IVR without writing the same
value to its WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.
The ISL95311 is pre-programmed with 40h in the IVR.
I
The ISL95311 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95311
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 1). On power-up of the ISL95311, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
WR: Wiper Register, IVR: Initial value Register.
2
non-volatile IVR.
to the WR and IVR of the DCP.
volatile WR.
volatile WR.
C Serial Interface
2
C interface operations must begin with a START
ADDRESS
2
1
0
TABLE 1. MEMORY MAP
NON-VOLATILE
IVR
2
C interface is conducted by
-
Reserved
VOLATILE
ACR
February 6, 2008
WR
FN8084.1