PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 205

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.2
The Timer3/5/7 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity
for each available source is also selectable and is
controlled by the TxGPOL bit (TxGCON <6>).
TABLE 15-2:
15.5.2.1
The TxG pin is one source for Timer3/5/7 gate control.
It can be used to supply an external source to the
Timerx gate circuitry.
15.5.2.2
The Timer4/6/8 register will increment until it matches
the value in the PRx register. On the very next increment
cycle, TMRx will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
FIGURE 15-3:
 2010 Microchip Technology Inc.
TxGSS<1:0>
Timer3/5/7
TMRxGE
TxGPOL
TxGVAL
TxG_IN
TxGTM
00
01
10
11
TxCKI
TIMER3/5/7 GATE SOURCE
SELECTION
TxG Pin Gate Operation
Timer4/6/8 Match Gate Operation
Timerx Gate Pin
TMR(x + 1) to Match PR(x + 1)
(TMR(x + 1) increments to match
PR(x + 1)
Comparator 1 Output
(Comparator logic high output)
Comparator 2 Output
(Comparator logic high output)
TIMER3/5/7 GATE SOURCES
N
TIMER3/5/7 GATE TOGGLE MODE
Timerx Gate Source
N + 1 N + 2 N + 3
Preliminary
PIC18F87K90 FAMILY
Depending on TxGPOL, Timerx increments differently
when TMR(x + 1) matches PR(x + 1). When
TxGPOL = 1, Timerx increments for a single instruction
cycle following a TMR(x + 1) match with PR(x + 1).
When TxGPOL = 0, Timerx increments continuously
except for the cycle following the match when the gate
signal goes from low-to-high.
15.5.2.3
The output of Comparator 1 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timerx will
increment depending on the transitions of the
CMP1OUT (CMSTAT<5>) bit.
15.5.2.4
The output of Comparator 2 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timerx will
increment depending on the transitions of the
CMP2OUT (CMSTAT<6>) bit.
15.5.3
When Timer3/5/7 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3/5/
7 gate signal, as opposed to the duration of a single
level pulse.
The Timerx gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see Figure 15-3.)
The TxGVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3/5/7 Gate Toggle mode is enabled by setting the
TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
N + 4
TIMER3/5/7 GATE TOGGLE MODE
Comparator 1 Output Gate Operation
Comparator 2 Output Gate Operation
N + 5 N + 6 N + 7
DS39957B-page 205
N + 8