PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 441

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.3.2
The difference in the two regulators’ operation arises
with Sleep mode. The ultra low-power regulator gives
the device the lowest current in the Regulator Enabled
mode.
The on-chip regulator can go into a lower power mode
when the device goes to Sleep by setting the REGSLP
bit (WDTCON<7>). This puts the regulator in a standby
mode so that the device consumes much less current.
The on-chip regulator can also go into the Ultra Low-
Power mode, which consumes the lowest current
possible with the regulator enabled. This mode is
controlled by the RETEN bit (CONFIG1L<0>) and
SRETEN bit (WDTCON<4>).
TABLE 28-3:
 2010 Microchip Technology Inc.
Note 1:
Regulator
Enabled
Enabled
Enabled
Enabled
Enabled
x = Indicates that V
OPERATION OF REGULATOR IN
SLEEP
SLEEP MODE REGULATOR SETTINGS
Normal Operation (Sleep)
Low-Power mode (Sleep)
Normal Operation (Sleep)
Low-Power mode (Sleep)
Ultra Low-Power mode (Sleep)
IT
status is invalid.
Power Mode
Preliminary
PIC18F87K90 FAMILY
WDTCON<7>
The various modes of regulator operation are shown in
Table 28-3.
When the ultra low-power regulator is in Sleep mode,
the internal reference voltages in the chip will be shut
off and any interrupts referring to the internal reference
will not wake up the device. If the BOR or LVD is
enabled, the regulator will keep the internal references
on and the lowest possible current will not be achieved.
When using the ultra low-power regulator in Sleep
mode, the device will take about 250  s, typical, to start
executing the code after it wakes up.
VREGSLP
(1)
0
1
0
1
x
WDTCON<4>
SRETEN
x
x
0
0
1
DS39957B-page 441
CONFIG1L<0>
RETEN
1
1
x
x
0