PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 561

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

 2010 Microchip Technology Inc.
Half-Bridge PWM Output .................................. 258, 265
High-Voltage Detect Operation (VDIRMAG = 1)....... 402
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD Interrupt Timing in Quarter
LCD Reference Ladder Power Mode Switching ....... 281
LCD Sleep Entry/Exit When SLPEN = 1 or
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 401
MSSP I
MSSP I
PWM Auto-Shutdown with
PWM Auto-Shutdown with Firmware Restart............ 264
PWM Direction Change ............................................ 261
PWM Direction Change at Near
PWM Output ............................................................. 246
PWM Output (Active-High)........................................ 256
PWM Output (Active-Low) ........................................ 257
Repeated Start Condition.......................................... 336
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................. 364
Slave Synchronization .............................................. 307
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode).......................................... 306
SPI Mode (Slave Mode, CKE = 0) ............................ 308
SPI Mode (Slave Mode, CKE = 1) ............................ 308
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Master Transmission
Synchronous Reception (Master Mode, SREN) ....... 367
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer Pulse Generation ............................................ 232
Timer0 and Timer1 External Clock ........................... 527
Timer1 Gate Count Enable Mode ............................. 192
Timer1 Gate Single Pulse Mode ............................... 194
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence ..................................... 340
C Bus Data ............................................................. 534
C Bus Start/Stop Bits.............................................. 533
C Master Mode (7 or 10-Bit Transmission) ............ 338
C Master Mode (7-Bit Reception)........................... 339
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 324
C Slave Mode (10-Bit Reception, SEN = 1) ........... 329
C Slave Mode (10-Bit Transmission)...................... 325
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 320
C Slave Mode (7-Bit Reception, SEN = 1) ............. 328
C Slave Mode (7-Bit Transmission)........................ 322
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ......... 340
ADMSK = 01001).............................................. 323
ADMSK = 01011).............................................. 321
(7 or 10-Bit Addressing Mode) .......................... 330
Duty Cycle Drive ............................................... 296
CS = 00............................................................. 297
Auto-Restart Enabled ....................................... 264
100% Duty Cycle .............................................. 262
Timer (OST) and Power-up Timer (PWRT) ...... 524
V
(STRSYNC = 1) ................................................ 268
(STRSYNC = 0) ................................................ 268
(Through TXEN) ............................................... 366
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
2
2
C Bus Data.................................................. 535
C Bus Start/Stop Bits .................................. 535
Rise > T
PWRT
DD
) ............................................. 71
, V
DD
DD
DD
), Case 1........................ 71
), Case 2........................ 71
Rise T
DD
,
PWRT
) ............... 70
Preliminary
PIC18F87K90 FAMILY
Timing Diagrams and Specifications
Top-of-Stack (TOS) Access................................................ 85
TSTFSZ ............................................................................ 489
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode........................................ 193
Timer3/5/7 Gate Count Enable Mode....................... 204
Timer3/5/7 Gate Single Pulse Mode......................... 206
Timer3/5/7 Gate Single Pulse/Toggle
Timer3/5/7 Gate Toggle Mode.................................. 205
Transition for Entry to Idle Mode ................................ 57
Transition for Entry to SEC_RUN Mode ..................... 53
Transition for Entry to Sleep Mode ............................. 56
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode................ 57
Transition for Wake from Sleep (HSPLL) ................... 56
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode...................................... 55
Type-A in 1/2 MUX, 1/2 Bias Drive........................... 286
Type-A in 1/2 MUX, 1/3 Bias Drive........................... 288
Type-A in 1/3 MUX, 1/2 Bias Drive........................... 290
Type-A in 1/3 MUX, 1/3 Bias Drive........................... 292
Type-A in 1/4 MUX, 1/3 Bias Drive........................... 294
Type-A/Type-B in Static Drive .................................. 285
Type-B in 1/2 MUX, 1/2 Bias Drive........................... 287
Type-B in 1/2 MUX, 1/3 Bias Drive........................... 289
Type-B in 1/3 MUX, 1/2 Bias Drive........................... 291
Type-B in 1/3 MUX, 1/3 Bias Drive........................... 293
Type-B in 1/4 MUX, 1/3 Bias Drive........................... 295
Capture/Compare/PWM Requirements.................... 528
CLKO and I/O Requirements.................................... 523
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 521
High/Low-Voltage Detect Characteristics ................. 526
I
I
Internal RC Accuracy (INTOSC)............................... 522
MSSP I
MSSP I
PLL Clock ................................................................. 522
Reset, Watchdog Timer, Oscillator Start-up Timer,
Timer0 and Timer1 External Clock
Ultra Low-Power Wake-up........................................ 537
2
2
C Bus Data Requirements (Slave Mode) ............... 534
C Bus Start/Stop Bits Requirements
Combined Mode ............................................... 195
Combined Mode ............................................... 207
(INTOSC to HSPLL) ......................................... 442
PRI_RUN Mode.................................................. 55
PRI_RUN Mode (HSPLL) ................................... 53
Requirements ................................................... 537
Requirements ................................................... 537
(Master Mode, CKE = 0)................................... 529
(Master Mode, CKE = 1)................................... 530
(Slave Mode, CKE = 0)..................................... 531
(CKE = 1).......................................................... 532
(Slave Mode) .................................................... 533
Power-up Timer and Brown-out
Reset Requirements......................................... 525
Requirements ................................................... 527
2
2
C Bus Data Requirements .......................... 536
C Bus Start/Stop Bits Requirements........... 535
DS39957B-page 561