PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 303

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 21-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
When enabled, these pins must be properly configured as inputs or outputs.
Bit combinations not specifically listed here are either reserved or implemented in I
WCOL: Write Collision Detect bit
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over-
0 = No overflow
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
1010 = SPI Master mode: Clock = F
0101 = SPI Slave mode: Clock = SCKx pin; SSx pin control disabled; SSx can be used as I/O pin
0100 = SPI Slave mode: Clock = SCKx pin; SSx pin control enabled
0011 = SPI Master mode: Clock = TMR2 Output/2
0010 = SPI Master mode: Clock = F
0001 = SPI Master mode: Clock = F
0000 = SPI Master mode: Clock = F
SSPOV
R/W-0
software)
flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
(1)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(2)
R/W-0
CKP
Preliminary
OSC
OSC
OSC
OSC
(1)
/8
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K90 FAMILY
SSPM3
R/W-0
(2)
(3)
SSPM2
R/W-0
(3)
(3)
x = Bit is unknown
SSPM1
R/W-0
2
C™ mode only.
(3)
DS39957B-page 303
SSPM0
R/W-0
bit 0
(3)