PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 554

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K90 FAMILY
Extended Instruction Set
External Oscillator Modes
F
Fail-Safe Clock Monitor............................................. 423, 443
Fast Register Stack............................................................. 87
Firmware Instructions........................................................ 449
Flash Program Memory..................................................... 109
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 470
H
Hardware Multiplier ........................................................... 125
High/Low-Voltage Detect .................................................. 399
HLVD. See High/Low-Voltage Detect. .............................. 399
DS39957B-page 554
ADDFSR ................................................................... 492
ADDULNK................................................................. 492
CALLW...................................................................... 493
MOVSF ..................................................................... 493
MOVSS ..................................................................... 494
PUSHL ...................................................................... 494
SUBFSR ................................................................... 495
SUBULNK ................................................................. 495
Clock Input (EC, ECPLL Modes) ................................ 46
HS, HSPLL.................................................................. 44
Exiting Operation ...................................................... 443
Interrupts in Power-Managed Modes ........................ 444
POR or Wake from Sleep ......................................... 444
WDT During Oscillator Failure .................................. 443
Associated Registers ................................................ 117
Control Registers ...................................................... 110
Erase Sequence ....................................................... 114
Erasing ...................................................................... 114
Operation During Code-Protect ................................ 117
Protection Against Spurious Writes .......................... 117
Reading..................................................................... 113
Table Pointer
Table Pointer Boundaries ......................................... 112
Table Reads and Table Writes ................................. 109
Unexpected Termination ........................................... 117
Write Sequence ........................................................ 115
Write Verify ............................................................... 117
Writing To.................................................................. 115
8 x 8 Multiplication Algorithms .................................. 125
Operation .................................................................. 125
Performance Comparison (table) .............................. 125
Applications............................................................... 402
Associated Registers ................................................ 403
Current Consumption ................................................ 401
Effects of a Reset...................................................... 403
Operation .................................................................. 400
Setup......................................................................... 401
Start-up Time ............................................................ 401
Typical Low-Voltage Detect Application.................... 402
EECON1 and EECON2 .................................... 110
TABLAT (Table Latch) Register........................ 112
TBLPTR (Table Pointer) Register ..................... 112
Boundaries Based on Operation....................... 112
During Sleep ..................................................... 403
Preliminary
I
I/O Ports............................................................................ 151
I
ID Locations.............................................................. 423, 448
INCF ................................................................................. 470
INCFSZ............................................................................. 471
In-Circuit Debugger........................................................... 448
In-Circuit Serial Programming (ICSP)....................... 423, 448
Indexed Literal Offset Addressing
Indexed Literal Offset Mode.............................................. 496
Indirect Addressing ........................................................... 103
INFSNZ............................................................................. 471
Instruction Cycle ................................................................. 88
2
C Mode (MSSP)
Open-Drain Outputs.................................................. 152
Output Pin Drive ....................................................... 151
Pin Capabilities ......................................................... 151
Pull-up Configuration ................................................ 151
Acknowledge Sequence Timing ............................... 340
Associated Registers ................................................ 346
Baud Rate Generator ............................................... 333
Bus Collision
Clock Arbitration ....................................................... 334
Clock Stretching........................................................ 326
Clock Synchronization and the CKP bit .................... 327
Effects of a Reset ..................................................... 341
General Call Address Support .................................. 330
I
Master Mode............................................................. 331
Multi-Master Communication, Bus Collision
Multi-Master Mode .................................................... 341
Operation .................................................................. 316
Read/Write Bit Information (R/W Bit) ................ 316, 319
Registers .................................................................. 311
Serial Clock (SCLx) .................................................. 319
Slave Mode............................................................... 316
Sleep Operation........................................................ 341
Stop Condition Timing .............................................. 340
and Standard PIC18 Instructions.............................. 496
Clocking Scheme........................................................ 88
Flow/Pipelining............................................................ 88
2
C Clock Rate w/BRG.............................................. 333
During a Repeated Start Condition................... 344
During a Stop Condition ................................... 345
10-Bit Slave Receive Mode (SEN = 1) ............. 326
10-Bit Slave Transmit Mode ............................. 326
7-Bit Slave Receive Mode (SEN = 1) ............... 326
7-Bit Slave Transmit Mode ............................... 326
Operation.......................................................... 332
Reception ......................................................... 337
Repeated Start Condition Timing ..................... 336
Start Condition Timing ...................................... 335
Transmission .................................................... 337
and Arbitration .................................................. 341
Address Masking Modes
Addressing........................................................ 316
Reception ......................................................... 319
Transmission .................................................... 319
5-Bit .......................................................... 317
7-Bit .......................................................... 318
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