ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 18
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ISP1564HLUM
Manufacturer Part Number
ISP1564HLUM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1564HLUM.pdf
(100 pages)
Specifications of ISP1564HLUM
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Compliant
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Table 8.
Table 9.
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15
14
13
12
11
10 to 9
8
7
6
Symbol
DPE
SSE
RMA
RTA
STA
DEVSELT
[1:0]
MDPE
FBBC
reserved
Status register (address 06h) bit allocation
Status register (address 06h) bit description
8.2.1.4 Status register
FBBC
DPE
15
R
R
0
7
0
Description
Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if
the parity error handling is disabled.
Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that
never assert SERR# do not need to implement this bit.
Received Master Abort: This bit must be set by a master device whenever its transaction, except for
special cycle, is terminated with master abort. All master devices must implement this bit.
Received Target Abort: This bit must be set by a master device whenever its transaction is
terminated with target abort. All master devices must implement this bit.
Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction
with target abort. Devices that never signal target abort do not need to implement this bit.
DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to
assert DEVSEL#:
00b — Fast
01b — Medium
10b — Slow
11b — Reserved
These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any
bus command, except Configuration Read and Configuration Write.
Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three
conditions are met:
Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting
fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to
logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise.
-
•
•
•
The Status register is a 2-byte read-only register used to record status information on PCI
bus-related events. For bit allocation, see
The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write.
The agent setting the bit acted as the bus master for the operation in which error occurred.
PER (bit 6 in the Command register) is set.
reserved
SSE
14
R
R
0
6
0
66MC
RMA
13
R
R
0
5
0
Rev. 01 — 4 December 2006
RTA
CL
12
R
R
0
4
1
Table
STA
11
R
R
0
3
0
8.
10
R
R
0
2
0
DEVSELT[1:0]
HS USB PCI Host Controller
reserved
R
R
9
1
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
MDPE
R
R
8
0
0
0
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