ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 26

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 32.
Address: Value read from address 34h + 0h
Legend: * reset value
Table 33.
Address: Value read from address 34h + 1h
Legend: * reset value
[1]
Table 34.
Address: Value read from address 34h + 2h
[1]
ISP1564_1
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Reset value for OHCI is 00h and for EHCI is E4h.
X is 0 for OHCI; X is 1 for EHCI.
Symbol
NEXT_ITEM_
PTR[7:0]
Symbol
CAP_ID[7:0]
Cap_ID - Capability Identifier register bit description
Next_Item_Ptr - Next Item Pointer register bit description
PMC - Power Management Capabilities register bit allocation
8.2.3.2 Next_Item_Ptr register
8.2.3.3 PMC register
15
R
R
1
7
1
AUX_C[1:0]
The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in
the function’s capability list. The value given is an offset into the function’s PCI
configuration space. If the function does not implement any other capabilities defined by
the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in
the list, then this register must be set to 00h. See
The Power Management Capabilities (PMC) register is a 2-byte register, and the bit
allocation is given in
function related to power management.
Access
R
Access
R
14
R
R
1
6
0
Value
01h*
Value
[1]
*
PME_S[4:0]
DSI
X
13
Description
ID: This field when 01h identifies the linked list item as being PCI power
management registers.
R
R
5
0
[1]
Table
Rev. 01 — 4 December 2006
Description
Next Item Pointer: This field provides an offset into the function’s PCI
configuration space, pointing to the location of the next item in the
function’s capability list.
34. This register provides information on the capabilities of the
reserved
12
R
R
1
4
0
PMI
X
11
R
R
3
0
[1]
Table
D2_S
33.
X
10
R
R
2
0
[1]
HS USB PCI Host Controller
VER[2:0]
D1_S
R
9
1
R
1
1
© NXP B.V. 2006. All rights reserved.
ISP1564
AUX_C
R
8
0
R
0
0
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