ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 30
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ISP1564HLUM
Manufacturer Part Number
ISP1564HLUM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1564HLUM.pdf
(100 pages)
Specifications of ISP1564HLUM
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Compliant
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Table 41.
Address: Value read from address 34h + 7h
Legend: * reset value
Table 43.
Address: Value read from address 34h + 8h
Legend: * reset value
ISP1564_1
Product data sheet
Bit
7 to 0
Bit
7 to 0
Symbol
VPD_CAP_ID[7:0] R
Symbol
DATA[7:0]
Data register bit description
VPD_Cap_ID - Vital Product Data Capability Identifier register bit description
8.2.3.6 Data register
8.2.4.1 VPD_Cap_ID register
8.2.4.2 VPD_Next_Item_Ptr register
8.2.4 VPD register
Table 40.
The Data register is an optional, 1-byte register that provides a mechanism for the
function to report state dependent operating data, such as power consumed or heat
dissipated.
Table 42.
The Capability Identifier (Cap_ID) register when read by the system software as 03h
indicates that the data structure currently being pointed to is the VPD_Data structure. The
bit description of the register is given in
The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in
the function’s capability list. The value given is an offset into the function’s PCI
configuration space. If the function does not implement any other capabilities defined by
the PCI-SIG for inclusion in the capabilities list, or if the power management is the last
item in the list, then this register must be set to 00h. See
Originating device’s
bridge PM state
D0
D1
D2
D3
D3
Access
R
Offset
Value read from address 34h + 8h
Value read from address 34h + 9h
Value read from address 34h + Ah
Value read from address 34h + Ch
hot
cold
Access Value Description
PCI bus power and clock control
VPD specific registers
Table 41
Value
00h*
03h*
VPD Capability ID: Capability structure ID; for details, refer to Appendix I of
PCI Local Bus Specification Rev. 2.2
shows the bit description of the register.
Secondary bus
PM state
B0
B1
B2
B2, B3
B3
Rev. 01 — 4 December 2006
Description
DATA: This register is used to report the state dependent data requested
by the D_S field of the PMCSR register. The value of this register is scaled
by the value reported by the DS field of the PMCSR register.
Register
Vital Product Data Capability Identifier (VPD_Cap_ID)
Vital Product Data Next Item Pointer (VPD_Next_Item_Ptr)
Vital Product Data Address (VPD_Addr)
Vital Product Data Data (VPD_Data)
Resultant actions by bridge (either direct or indirect)
none
none
clock stopped on secondary bus
clock stopped and PCI V
bus (B3 only); for definition of B2_B3#, see
none
Table
43.
Table
HS USB PCI Host Controller
CC
removed from secondary
44.
© NXP B.V. 2006. All rights reserved.
ISP1564
Table
39.
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