ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 51

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 74.
Address: Content of the base address register + 30h
Table 75.
Address: Content of the base address register + 34h
[1]
ISP1564_1
Product data sheet
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
Symbol
DH[27:0]
reserved
HcDoneHead - Host Controller Done Head register bit description
HcFmInterval - Host Controller Frame Interval register bit allocation
11.1.14 HcFmInterval register
R/W
R/W
R/W
R/W
FIT
31
23
15
0
0
0
7
1
reserved
Description
Done Head: When a TD is completed, the Host Controller writes the content of HcDoneHead to the
NextTD field of the TD. The Host Controller then overwrites the content of HcDoneHead with the
address of this TD. This is set to logic 0 whenever the Host Controller writes the content of this
register to HCCA.
-
This register contains a 14-bit value that indicates the bit time interval in a frame, that is,
between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum
packet size that the Host Controller may transmit or receive, without causing a scheduling
overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new
value over the present at each SOF. This provides the possibility for the Host Controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset. The bit allocation of the register is given in
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
1
R/W
R/W
R/W
R/W
29
21
13
0
0
1
5
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
1
FSMPS[7:0]
FI[7:0]
FSMPS[14:8]
R/W
R/W
R/W
R/W
27
19
11
0
0
1
3
1
FI[13:8]
Table
75.
R/W
R/W
R/W
R/W
26
18
10
0
0
1
2
1
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
1
1
1
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
1
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