IDT77305L15PF IDT, Integrated Device Technology Inc, IDT77305L15PF Datasheet - Page 10

• Manufacturer Part Number: IDT77305L15PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77305L15PF

• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

mux select lines provide user control of FIFO selection.
SINGLE DEVICE OPERATION
Utopia Receive (UtopiaRx) and Utopia transmit (UtopiaTx). Both modes
can concentrate four nine-bit channels (up to 720 Mbs) to one 18-bit output
channel (up to 1.44 Gbs). In a building block implementation, multiple
streams over 10 Gbs (with 32, 64, or 128 bit buses) can be obtained. Mode
one, UtopiaRx, follows UtopiaRx protocols; and Mode two, UtopiaTx,
follows UtopiaTx protocols. The Receive/Transmit Select (RTS) pin sets
the UtopiaFIFO into the desired mode. The difference between these
modes relates to the Utopia specification for signal handshaking. In
UtopiaRx mode, the device receiving data controls the data flow through
ENR (or ENS on the output side). In UtopiaTx mode, the device sending
data controls the data flow through ENR (or ENS on the output side). This
is described in the Utopia ATM-PHY Level2 version 1 Document.
However, for applications other than ATM the cell size can be programmed
through the cell size register. Programming this register allows cell sizes
from 8 bytes to 128 bytes. With RST and OE both HIGH, CR(0-3), CSS,
ECT and CRC are cell size inputs. The default cell size of 53 bytes is
selected when both RST and OE are LOW. In either case the values
are latched on the rising edge of RST. To load a specific cell size value
from 8 bytes to 128 bytes use CR(0-3), CSS, ECT and CRC as inputs with
RST and OE both HIGH. The bit order is CR0, CR1, CR2, CR3, CSS,
ECT, CRC, with CR0 being LSB and CRC being MSB. Set all input pins
LOW to program a cell size of 128 bytes. See Table 1 for cell size
programming truth table.
CLAVR, ENR and SOCR (see Table 2a). Prior to cell transfer, the
controlling agent (data source for transmit mode, data destination for
receive mode) is notified a cell transfer can take place through the assertion
of the CLAVR signal. Each data transfer of a cell is completed by assertion
of ENR. The ENR signal is supplied by the controlling agent. During the
first data byte transfer, the data source asserts SOCR to mark the beginning
of the cell. Data transfer continues until the cell is completed. When the cell
size is reached, further writes are blocked until new CLAVR and SOCR
signals are received.
RXMODE
device and assertion of ENR results in data writes to the UtopiaFIFO in a
pipelined fashion. Once enabled, data is written on the following rising clock
edge. CLAVR controls data from the sender side. While this signal remains
HIGH, data is valid. If CLAVR goes LOW, data continues to be valid after
cell transfer is started. After cell transfer begins, if ENR is deasserted, data
writes halt until subsequent assertions (see Figures 3).
and UtopiaTx modes in either Master or Slave configuration. As a stand-
alone device, the UtopiaFIFO has The I/O status of the output pins are listed
in Table 3 for both UtopiaRx and UtopiaTx modes in either Master or
Slave configuration. As a stand-alone device, the UtopiaFIFO has
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
The two programmable interface signaling modes of operation are
Control signals for the input data (receive) side consists of
In UtopiaRx mode (see Figure 2a), ENR is an output to the sending
The I/O status of the output pins are listed in Table 3 for both UtopiaRx
In either mode, data is transferred in "cells". ATM cell size is 53 bytes.
10
the same description as shown for a device in a master setting—the
MSE signal is set HIGH (slave operation is described later in building
block mode section).
signaling a complete cell can be transferred. As the controlling
agent, the UtopiaFIFO asserts an output signal, ENS to transfer data
on the same rising clock edge (see Figure 6).
ADDITIONAL CONTROL SIGNALS—RX AND TX MODES
The global reset (RST) pin clears all register values. The byte swapping
(SWP) pin provides the ability to swap byte positions on the output. SWP
is a dynamic signal—once this signal is changed, output high and low bytes
are swapped on the next clock cycle. If SWP is high the first byte of data
is put in the upper byte of output bus, and if low the first byte is placed in
the lower byte. SWP high will make the output bus Utopia compliant. The
function is disabled when output bus size is set to 9-bits. The Byte Delete/
Insert (BDI) pin enables byte delete/insert to comply with ATM bus
matching. The input bus is Utopia compliant 9-bit bus with the output an 18-
bit bus. Data is transferred to each FIFO in 53 byte cells. The Utopia spec
defines 53 bytes per cell for 8-bit transfer and 54 bytes per cell for 16 bit
transfer. Compatibility with 53 byte ATM cell formatting during bus matching
is maintained. With the BDI selected, depending on the byte size and
interface signaling mode, the UtopiaFIFO will automatically insert and/or
delete dummy or header bytes according to Table 4; thus maintaining data
integrity and Utopia specification compatibility. With BDI asserted HIGH, cell
size is limited to 126 bytes. When output bus size is set to 9-bits, BDI must
be deasserted LOW.
to output data. The sequencer is enabled by asserting the Round
Robin Enable (RRE) HIGH. The sequencer will poll each FIFO in turn
to determine which has data to send and selects the appropriate FIFO.
In UtopiaTx mode, the CLAVS is an input to the UtopiaFIFO
Three additional control signals provide added device functionality.
The round robin sequencer sequentially selects one of four FIFOs
OE
0
0
1
1
Note values are loaded on the rising edge of RST
TABLE 1: Truth table for cell size programming
RST
Commercial and Industrial Temperature Ranges
0
0
1
1
CR(0-3), CSS, ECT, CRC are cell size inputs
sets default cell size of 53 bytes
CR(0-3), CSS ECT, CRC are tristated
CR(0-3), CSS, ECT, CRC are outputs
CR(0-3) = "0" then no cell in FIFO
CSS = no function: don't care
ECT asserts one cycle before the end of a cell
CRC = "0" then no FIFO(s) has a cell
CRC = "1" then at least one FIFO has cell
transfer
= "1" then cell in FIFO
FUNCTION
Preliminary
3206 tbl 14