IDT77305L15PF IDT, Integrated Device Technology Inc, IDT77305L15PF Datasheet - Page 13

• Manufacturer Part Number: IDT77305L15PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77305L15PF

• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The selection process begins one cycle prior to the completion of
the current FIFOs cell transfer (as defined by the Cell Size Register).
On one cycle, the UtopiaFIFO determines if a FIFO has a cell and
its identity. If a cell is ready, the counter will hold the value and present
it to the output of the mux select lines prior to the last word transfer of
the
state machine.
become inputs defining which FIFO will transfer data. Interrogation of the
select signals will take place at the beginning of each clock cycle. Four cell
ready pins (CR0-3) are provided so it can be determined if the port being
and assert the output CLAVS signal. See Figure 7 for round robin
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
If the RRE signal is deasserted LOW, the mux select lines and LDM
CLAVR
CLAVR
SOCR
Clock
SOCR
ENR
Data
DATA
ENR
Rx Mode
Utopia
FIFO
2a
current
RX
O
I
I
I
I
Receiver (Input)
Figure 2. Signal and Data I/O Directions for Rx, Tx Modes.
I/O
CLAVS
SOCS
DATA
ENS
TX
O
I
I
I
I
3206 tbl 15
cell
13
polled has a cell ready to transfer. With OE set LOW, CR0-3 signals
indicate cell available for the four FIFOs. If a particular FIFO has a
complete cell ready for output, the appropriate CR pin is asserted
HIGH. All four FIFOs cell ready signals are independent of each
other. CR-0, 1, 2, 3, signal cell available status for FIFO-A, B, C, D
respectfully. The Cell Ready Composite (CRC) signal is a composite
of all CR-n signals. If any of the FIFOs have a cell available, CRC is
asserted HIGH. CRC and CR(0-3) de-assert LOW on the last byte of
the current cell transfer, if there is not another complete cell to
transfer.
transfer the Load Mux (LDM) is asserted HIGH while that address is on
Once it has been determined that a particular FIFO has a cell to
CLAVR
SOCR
Clock
ENR
Data
CLAVR
SOCR
DATA
ENR
Commercial and Industrial Temperature Ranges
Tx Mode
Utopia
Tx Mode
FIFO
RX
O
O
O
I
I
2b
Receiver (Input)
I/O
CLAVS
SOCS
DATA
ENS
3206 drw 07
TX
O
O
O
I
I
3206 tbl 16