IDT77305L15PF IDT, Integrated Device Technology Inc, IDT77305L15PF Datasheet - Page 15

• Manufacturer Part Number: IDT77305L15PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77305L15PF

• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

All first Rank UtopiaFIFOs are set as Masters with the second Rank
having one Master and one Slave. The master/slave control signal-
ing for the Rx mode is shown in Figure 10c. After the Mux select
signals are set, they are loaded into the Slave from the Master on the
LDM rising clock edge. Once the mux signals are loaded either
externally or internally via Round Robin Sequencer, the CLAVS from
either Rank 1 or Rank 2 devices goes HIGH once a cell is available.
The receiving system must issue an active ENS signal once it can
accept a cell. When the CLAVS from Rank 2 and the receiving ENS
signal are both asserted, data will be put on the output bus (from both
the Master and Slave devices) on the clock cycle following assertion
of ENS. In this setup, ENS from the receiving system MUST be
asserted when it can accept data regardless of the CLAVS signals (the
target must not monitor CLAVS before asserting ENS). As shown in Figure
10c, if ENS is low prior to CLAVS assertion, then once CLAVS is asserted,
data is placed on the 36-bit bus on the same cycle. If CLAVS is asserted
before ENS, then once ENS is active, data is placed on the output bus on
the next cycle. With the first output word, SOCS is asserted for one cycle.
Data is synchronized between the Master and Slave internally. The Master
will assert LDM and Mux1 and Mux2 to the Slave two cycles prior to data
transfer to allow the Slave time to transfer data through internal registers;
it places data on the output bus two cycles later. The receiving system can
throttle data via the ENS signal.
BUILDING BLOCK MODE: 16 CHANNELS TO ONE 36-BIT
OUTPUT CHANNEL FOR TX SIGNALS
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
Mode
In transmit Utopia mode, the data transmitter controls data flow. For the
2
3
4
5
6
1
Tx/Rx Mode
Don't Care
Don't Care
Tx
Rx
Tx
Rx
Byte Size
Even
Even
Even
Odd
Odd
Odd
Ins/Del Selected
0
0
1
1
1
1
15
case of 16 channels to one 36-bit output channel, the second rank
of UtopiaFIFOs controls data flow to the downstream system via the
ENS signals. The data flow from rank 1 to rank 2 is controlled by rank
1. Data flow into rank 1 is controlled by the upstream system as
described earlier for a single device mode. This signal control is
shown in Figure 10d. Initially, the Mux select lines for the Master
(either via round robin or through external selection) are selected
and then loaded into the Slave on the rising edge of LDM. Once both
ENS from the Master and CLAVS from the receiver are asserted,
valid data is placed on the bus in 2 cycles. Data from the Slave is
placed on the bus two cycles after the LDM signal is received and
when CLAVS is asserted. For the first data word, SOCS is asserted.
Until an entire cell is transferred, CLAVS can be HIGH or LOW. The
transmitting device starts to monitor the CLAVS signal four cycles prior to
a completed cell transfer. If the receiving device (either downstream system
or rank 1 or rank 2 devices) cannot accept another cell transfer, it must de-
assert the CLAVS signal no later than this cycle. The Utopia FIFO devices
will determine if a second cell can be sent on the second cycle prior to last
word transfer.
prior to the end of current cell transfers are ignored. A counter keeps track
of byte transfer. If a "short cell" occurs (where a SOCR signal is received
prior to the end of cell transfer), the SOCR is ignored and the data from
the next incoming cell is loaded into the existing "short cell" until it is filled
to normal cell size. Any additional bytes from the incoming cell are ignored.
The short cell and next subsequent cell contents are bad data. Recovery
occurs on the third incoming cell. If a "long cell" occurs (where the number
of bytes exceeds the defined cell size and no new SOCR signal received
indicating a new cell), the extra bytes are ignored by the UtopiaFIFO. The
FIFO receiving the long cell will wait for a new SOCR (and assertion of
ENR and CLAVR) before continuing data transfer.
No added or deleted bytes
Byte insert to last high byte position
Delete byte 5, insert byte to last high byte position
Insert byte 6, insert byte to last high byte position
Delete byte 5
Insert byte 6
After the start of cell signal (SOCR) is received, future SOCR assertions
Commercial and Industrial Temperature Ranges
Result
3206 tbl 18