IDT77305L15PF IDT, Integrated Device Technology Inc, IDT77305L15PF Datasheet - Page 4

• Manufacturer Part Number: IDT77305L15PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77305L15PF

• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
SOCR a
SOCR b
SOCR c
SOCR d
WCLK
SOCS
Name
MUX2
RCLK
MUX1
MSE
SWP
RST
XOE
LDM
RRE
RTS
V
OE
Qn
CC
I/O
I/O
I/O
I/O
____
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Load Mux. RRE = "1" and MSE = "1": LDM is an output telling Slave to latch the Mux select address on the next
clock cycle, RRE = "0" and MSE = "1": LDM is an input that latches the Mux address for the next cell transfer.
Master/Slave Enable. MSE = "1" master mode, MSE = "0" slave mode.
MUX1 address. With RRE = "1": MUX1 outputs FIFO address LSB: with RRE = "0": MUX1 is input address LSB of
selected FIFO.
MUX2 address. With RRE = "1": MUX2 outputs FIFO address MSB: with RRE = "0": MUX2 is input addre MSB of
selected FIFO.
Output Enable. In combination with RST, it sets CR0-3 as either output cell available signals, input cell size values or
Data bus output.
Data read clock.
Round Robin Enable. RRE = "1" round robin sequencer enabled. RRE = "0" sets mux select lines and LDM as
inputs to provide user control over selected FIFO.
Reset. Clears all FIFO memory locations, read/write pointers, RR sequencer.
Receive/Transmit mode Selection RTS = "0" Utopia Rx mode, RTS = "1" UtopiaTx mode.
Start Of Cell (FIFO-a)—Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start Of Cell (FIFO-b)—Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start Of Cell (FIFO-c)—Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start Of Cell (FIFO-d)—Receive side. Active on first byte when CLAVR and ENR are asserted. After first byte read,
SOCR is ignored until full cell has been received.
Start of Cell (sender side). Assertion: first word is currently on output bus.
Swap Enable. Swaps high byte and low byte of current word. SWP = "0": First word is placed in lower byte (Q0-Q7)
of 16-bit output (little endian), SWP = "1": first word is placed in upper byte (Q9-Q16) of 16-bit output (big endian
Utopia compliant cell format).
Logic and supply V
Data write clock.
Data bus output enable.
tri-state outputs (see Table 1).
CC
.
4
Description
Commercial and Industrial Temperature Ranges
Preliminary
3206 tbl 02