IDT77305L15PF IDT, Integrated Device Technology Inc, IDT77305L15PF Datasheet - Page 14

• Manufacturer Part Number: IDT77305L15PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77305L15PF

• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

the Mux1 and Mux 2 lines. This will latch the address. There must be
a cell to transfer in the selected FIFO once LDM is asserted, as a new
FIFO port address cannot be selected until a cell is read from the
currently selected FIFO port. LDM is an input when RRE is LOW
the first word of the cell. ECT will de-assert LOW on the fourth to last word
of the cell.
is accomplished by using the device as a building block. Multiple UtopiaFIFOs
are interconnected to supply the desired bus widths and streams to be
merged. Widths up to 128 bits and 32 channels are possible. Figures 8 and
9 show the control signals between Master and Slave devices and the
downstream "target system" for 4 independent 9-bit channels merging to
one 36-bit output bus.
setup, the RRE must be disabled, and all output side control lines are inputs
or not connected. As shown in Figure 8, in UtopiaRx mode, the "target"
device receiving data sends the ENS signals to the Master and Slave.
Output data from each UtopiaFIFO is available on the output bus on the
following rising clock edge. The SOCS signal originates from the Master
to alert the receiving device that respective bytes start a new cell for both
UtopiaFIFOs. The MUX lines are inputs from the Master. The Master's
(disabled), regardless of the condition of MSE.
IDT77305
UtopiaFIFO™ 4 to 1 (128 x 9 x 4) Multiplexer-FIFO
The End of Cell Transfer (ECT) flag asserts HIGH with SOCS on
Combining more than four data flows and/or using larger bus widths
The Slave UtopiaFIFO output pin status is shown in Table 3. In this
RR Status
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Master/Slave Status
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Pin Name
CLAVS
CLAVS
CLAVS
CLAVS
SOCS
SOCS
SOCS
SOCS
MUX
MUX
MUX
MUX
ENS
ENS
ENS
ENS
14
CLAVS notifies the receiving device that both Master and Slave
UtopiaFIFOs have cells available for transfer.
Master and is an input to the receiving device. On each assertion of
ENS, data from both UtopiaFIFOs is presented to the respective
output buses on the same clock cycle. The SOCS signal originates
from the Master to alert the receiving device that byte starts a new cell
for both UtopiaFIFOs. The receiving device sends a CLAVS to the
Master and Slave to signal it can accept a new cell from both Master
and Slave devices.
is shown in Figure 10a. Here, the first rank of UtopiaFIFOs are connected
with their output low bytes each connected to 2nd rank UtopiaFIFO-5 and
all output high bytes connected as inputs to 2nd rank UtopiaFIFO-6. This
allows 16 (155 Mbs) channels to be multiplexed onto one 36-bit output bus
(2.4Gbs).
output channel.
BUILDING BLOCK MODE: 16 CHANNELS TO ONE 36-BIT
OUTPUT CHANNEL FOR RX SIGNALS
UtopiaFIFOs ENS inputs within Rank 2 (as shown in Figure 10b). As a
result, a deasserted ENS will prevent data transfer from rank 2 to the target
system. Data can only transfer in a pipelined fashion when ENS is active.
In UtopiaTx mode (see Figure 9), the ENS originates from the
An example of a sixteen (9-bit) channel to one (36-bit) output channel
Figure 11 shows sixteen 9-bit channels multiplexed onto one 18-bit
The target system ENS signal in an Rx protocol feeds into all
Commercial and Industrial Temperature Ranges
Rx Mode I/O
(not allowed)
(not allowed)
(not allowed)
(not allowed)
N/C-case D
N/C-case D
O-case B
O-case B
O-case B
I-case B
I-case D
I-case D
O
O
I
I
Tx Mode I/O
(not allowed)
(not allowed)
(not allowed)
(not allowed)
N/C-case C
N/C-case C
O-case A
O-case A
O-case A
I-case A
I-case C
I-case C
Preliminary
O
O
I
I
3206 tbl 17