PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 181

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

6.2.1.3
The VIPCMR0-2 registers contain command information dedicated to the VIP 0, 1, 2
(only the VIPCMR0 is shown here, VIPCMR1 and VIPCMR2 have the same structure).
VIPCMR Register
Reset value: 0000
WR_n
REFSEL(2:0)
EXREF
Data Sheet
15
7
x
VIP Command Registers (VIPCMR0, VIPCMR1, VIPCMR2)
DELCH(2:0)
Write Command to VIP_n (S/T, U
0 =
1 =
Reference Clock Channel Select (LT-T)
The reference clock signal for the DELIC oscillator is generated from
the internal VIP_n Channel_m coded in these 3 bits and passed on via
pin REFCLK to the next cascaded VIP or directly to the DELIC
000 =
001 =
...
007 =
External Reference Clock Selection (LT-T)
H
14
x
6
Data sent to VIP_n is invalid
Data sent to VIP_n is valid
Reference clock provided by Channel_0
Reference clock provided by Channel_1
Reference clock provided by Channel_7
13
5
x
EXREF
12
4
x
write
164
RD_n
PN
11
3
)
REFSEL (2:0)
PLLPPS SH_FSC DELRE
10
2
Register Description
Address:
VIPCMR0:
D0A8
VIPCMR1:
D0A9
VIPCMR2
D0AA
9
1
PEB 20570
PEB 20571
H
H
H
2003-07-31
WR_n
H
:
8
0