PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 182

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

DELCH(2:0)
DELRE
SH_FSC
PLLPPS
RD_n
Data Sheet
0 =
1 =
Delay Measurement Channel Selection (U
Selects one of the eight U
the delay is to be measured.
000 =
001 =
...
111 =
Delay Counter Resolution (U
Resolution of the delay counter.
0 =
1 =
Short FSC Pulse
0 =
1 =
PLL Positive Pulse Sensing
0 =
1 =
Read Request to VIP Status Register S_n (S/T, U
0 =
No external reference clock source. Reference clock is
generated
REFCLK(2:0) and passed on via REFCLK pin to VIP_n-1 or
directly to DELIC.
Reference clock is generated from external source via pin
INCLK and passed on via REFCLK pin to VIP_n-1 or directly to
DELIC. The internal reference clock generation logic is
disabled.
Note that VIP_0 has the highest priority in terms of clock
selection
Delay is measured in U
Delay is measured in U
Delay is measured in U
Resolution of 65 ns (15.36 MHz period)
Resolution of 130 ns (7.68 MHz period)
Note: Using a resolution of 65 ns, the maximum delay of
The next FSC frame is no superframe
The next FSC is assumed as superframe
Normal operation
The clock recovering PLLs of all VIP channels operate on
positive line pulses only
No register read
20.8 µs is not covered (refer to DELAY(7:0) bits)
from
PN
165
internal
PN
line interface channels of each VIP where
)
PN
PN
PN
Channel_0
Channel_1
Channel_7
VIP_n
PN
)
channel
Register Description
PN
)
specified
PEB 20570
PEB 20571
2003-07-31
in