PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 230

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

6.2.6.15 GHDLCU Frame Frequency
ST2 Register
Reset value: xxxx xx00 xxxx xxxx
OUSER1
OUSER0
1)
Data Sheet
This bit has to be set once during initialization for single scrambling mode. If mixed scrambling mode is used
(e.g. DASL/OCTAT-P) the following has to be done: When accessing the HRAM this bit has to be reset (’0’)
before enabling descrambler/scrambler it has to be set (’1’).
15
7
x
x
0 =
1 =
0 =
1 =
14
x
6
x
16 kHz GHDLCU frame frequency
96 kHz GHDLCU frame frequency
Test mode
write access to HRAM-0 is enabled
write access to HRAM-1, HRAM-2 is disabled
write access to HRAM0, HRAM-1, HRAM-2 is enabled
13
x
5
x
B
12
OAK: write
x
4
x
213
11
3
x
x
10
x
2
x
Address: DSP-register
Register Description
OUSER1 OUSER0
9
1
x
PEB 20570
PEB 20571
1)
2003-07-31
8
0
x