PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 260

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

6.2.11.12 Strap Status Register
Strap Status Register (CSTRAP)
Reset value: 0000 0xxx xxxx xx10
Note: ’x’ = unused bits, read as 0
Note: .
STRAP
(10:0)
Data Sheet
15
7
x
bit 10
bit 9:7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
This register enables the OAK to read the straps values, as sampled
during reset
14
6
x
PCM Clock Master Strap
Test Mode Strap
Emulation Boot Strap
PLL Bypass Strap
DSP PLL Power-Down Strap
Boot Strap
Reset counter Bypass Strap
DCXO Fast-Synchronization Enable (read/write)
0 =
1 =
Internal Source Clock Strap (read/ write)
0 =
1 =
13
5
x
Linear (slow) synchronization (for DECT applications)
Fast synchronization (default)
PFS, PDC, DCL, FSC, DCL2000 are delayed by some
ns (default)
PFS, PDC, DCL, FSC, DCL2000 are not delayed
B
12
x
4
STRAP(7:0)
read/ write
243
11
3
x
10
2
STRAP(10:8)
Register Description
Address: D08F
9
1
PEB 20570
PEB 20571
2003-07-31
8
0
H