PEB20570FV31XP Infineon Technologies, PEB20570FV31XP Datasheet - Page 84

• Manufacturer Part Number: PEB20570FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV31XP

• Lead Free Status / Rohs Status: Compliant

3.5
The DELIC provides fully IEEE Standard 1149.1 compatible boundary scan support to
allow cost effective board testing. It consists of:
• Complete boundary scan test
• Test access port controller (TAP)
• Five dedicated pins: JTCK, TMS, TDI, TDO (according to JTAG) and an additional
• One 32-bit IDCODE register
3.5.1
Depending on the pin functionality one or two boundary scan cells are provided.
Pin Type
Input
Output
When the TAP controller is in the appropriate mode data is shifted into/out of the
boundary scan via the pins TDI/TDO using a clock of up to 6.25 MHz on pin JTCK.
The sequence of the DELIC pins can be taken from the BSDL files.
3.5.2
The Test Access Port (TAP) controller implements the state machine defined in the
JTAG standard IEEE 1149.1. Transitions on the pin TMS cause the TAP controller to
perform a state change.
The TAP controller supports a set of 5 standard instructions:
Table 26
Code
0000
0001
0010
0011
1111
Data Sheet
TRST pin to enable asynchronous resets to the TAP controller
JTAG Test Interface
Boundary Scan Test
TAP Controller
Instruction
EXTEST
INTEST
SAMPLE/PRELOAD
IDCODE
BYPASS
TAP Controller Instruction Codes
1
Number of Boundary Scan Cells
2
Function
External testing
Snap-shot testing
Bypass operation
Internal testing
Reading ID code register
67
Usage
Input
Output, enable
Interface Description
PEB 20570
PEB 20571
2003-07-31