PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 136
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PEF2054NV21XK
Manufacturer Part Number
PEF2054NV21XK
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF2054NV21XK.pdf
(269 pages)
Specifications of PEF2054NV21XK
Lead Free Status / Rohs Status
Compliant
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W:MACR =
Table 22
MOC3 … 0
0000
0001
0011
0010
0111
0110
0101
0100
W:MACR = 1000 0000
The Procedure for Writing to the Upstream DM Data Field is
W:MADR = value to be transmitted in the PCM (sub)time slot
W:MAAR = address of the desired (upstream)
MOC3 … 0 defines the bandwidth and the position of the subchannel according to
table 22.
The Procedure for Reading the DM Data Field is
W:MAAR = address of the desired PCM time slot encoded according to figure 48
wait for STAR:MAC = 0
R:MADR = value
Figure 49 illustrates the access to the Data Memory Data Field.
1)
2)
Semiconductor Group
The U/D bit of MAAR will implicitly be set to 1.
When reading a DM data field location, all 8 bits are read regardless of the bandwidth selected by the MOC
bits.
figure 48
bit 7
0
B
MOC3
= 80
H
Transferred Bits
–
bits 7 … 0
bits 7 … 4
bits 3 … 0
bits 7 … 6
bits 5 … 4
bits 3 … 2
bits 1 … 0
2)
MOC2
136
MOC1
1)
PCM time slot encoded according to
MOC0
Channel Bandwidth
–
64 kbit/s
32 kbit/s
32 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
0
Application Hints
0
PEB 2055
PEF 2055
bit 0
0
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