PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 28

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

request can be determined by reading the ISTA register.
The INT output is level active. It remains active until all interrupt sources have been
serviced. If a new status bit is set while an interrupt is being serviced, the INT remains
active. However, for the duration of a write access to the MASK-register the INT line is
deactivated. When using an edge-triggered interrupt controller, it is thus recommended
to rewrite the MASK register at the end of any interrupt service routine.
Every interrupt source can be selectively masked by setting the respective bit of the
MASK register. Such masked interrupts will not be indicated in the ISTA register, nor will
they activate the INT line.
2.2
The PCM interface formats the data transmitted or received at the PCM highways. It can
be configured to provide one (max. 8.192 Mbit/s), two (max. 4.096 Mbit/s) or four (max.
2.048 Mbit/s) PCM-ports, consisting each of a data receive (RxD), a data transmit (TxD)
and an output tristate indication line (TSC).
The PCM interface is supplied with a frame signal (PFS) and a PCM clock (PDC). To
properly clock the PCM interface, a PDC signal with a frequency equal or twice the data
rate has to be applied to the EPIC.
Port configuration, data rates, clock shift and sampling conditions are programmable.
In order to simplify the use of 8- and 16-bit Siemens / Intel type CPUs, different register
addresses are defined in multiplexed and demultiplexed bus mode (see chapter 4.1). In
the multiplexed mode even addresses are used (AD0 always 0).
For a demultiplexed P interface mode the OMDR:RBS bit is needed in addition to the
address lines A3 .. A0. With OMDR:RBS (register bank selection) one of two register
banks is selected.
RBS = “1” selects a set of registers used for device initialization (e.g. CFI and PCM
interface initialization).
RBS = “0” switches to a group of registers necessary during operation (e.g. connection
programming).
The OMDR register containing the RBS bit can be accessed with either value of RBS.
Interrupts
An interrupt of the EPIC is indicated by activating the INT line. The detailed cause of the
Semiconductor Group
PCM Interface
28
Functional Description
PEB 2055
PEF 2055