PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 178

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

After these programming steps, the control memory will have the following content:
Figure 65
Control Memory Contents for Decentral D-Channel Handling
Central D-Channel Handling Scheme
This option applies for IOM channels where the even time slot consists of an 8 bit monitor
channel and the odd time slot of a 2 bit D-Channel followed by a 4 bit C/I channel
followed by the 2 monitor handshake bits MR and MX.
The monitor channel is handled by the MF handler according to the selected protocol,
handshake or non-handshake. If the handshake option is selected (IOM-2), the MF
handler controls the MR and MX bits according to the IOM-2 specification. If the
non-handshake option is selected (IOM-1), the MF handler sets both MR and MX bits to
Semiconductor Group
Up-
stream
Down-
stream
CFI
Frame
0
127
0
127
P0, TS2
P0, TS3
P0, TS2
P0, TS3
0
1
1
1
Code Field
0
0
0 0
0 1
178
0
0
0
0
0
1
Control Memory
X
X
1
1
X X X X X X X
X
1
1
0
X
1
C/I Value
C/I Value
Data Field
X
0
1
0
X
1
X
0
Application Hints
1
ITD08080
X
1
1 1
X
1
PEB 2055
PEF 2055