PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 60

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

Semiconductor Group
4.2.2.6 Configurable Interface Subchannel Register (CSCR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
SC#1..#0 CFI Subchannel Control for logical port #.
Note: In CFI-mode 1:
bit 7
SC31
In CFI-mode 2:
In CFI-mode 3:
The subchannel control bits SC#1..SC#0 specify separately for each logical
port the bit positions to be exchanged with the data memory (DM) when a
connection with a channel bandwidth as defined by the CM-code has been
established:
SC#1
0
0
1
1
SC30
H
SC#0
0
1
0
1
SC21
SC31 = SC21 = SC11 = SC01; SC30 = SC20 = SC10 = SC00
SC21 = SC01; SC20 = SC00; SC31 = SC11; SC30 = SC10
SC0x control ports 0 and 4; SC1x control ports 1 and 5;
SC2x control ports 2 and 6; SC3x control ports 3 and 7
Bit Positions for CFI Subchannels
having a Bandwidth of
64 kbit/s
7..0
7..0
7..0
7..0
SC20
60
SC11
read/write
read/write
32 kbit/s
7..4
3..0
7..4
3..0
Detailed Register Description
SC10
OMDR:RBS = 1
address: 36
address: B
SC01
16 kbit/s
7..6
5..4
3..2
1..0
PEB 2055
PEF 2055
H
bit 0
H
SC00