PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 226

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

used to supervise the clock and framing signals for missing or additional clock cycles.
The EPIC internally checks the PFS period against the duration expected from the
programmed clock rate. The clock rate corresponds to the frequency applied to the PDC
pin. The number of clock cycles received within one PFS period is compared with the
values programmed to PBNR (number of bits per frame) and PMOD:PCR (single/double
clock rate operation). If for example single clock rate operation with 24 time slots per
frame is programmed, the EPIC expects 192 clock cycles within one PFS period. The
synchronous state is reached after the EPIC has detected two consecutive correct
frames. The synchronous state is lost if one erroneous frame is found. The
synchronization status (gained or lost) can be read from the STAR register (PSS bit) and
each status change generates an interrupt (ISTA:PFI).
It should be noted that the framing supervision function is optional, i.e. it is also allowed
to apply a PFS signal having a period of several frame periods e.g. 4 kHz, 2 kHz, … .
The STAR:PSS bit will then be at logical 0 all the time, which does however not affect
the proper operation of the EPIC.
Figure 78
Connection of Redundant PCM Transmission Lines to the EPIC
5.8.3
Usually the repetition rate of the applied framing pulse PFS is identical to the frame
period (125 s). If this is the case, the ’loss of synchronism indication function’ can be
Semiconductor Group
EPIC
OUT0
TSC0
IN0
PMOD AIS0
ISTA PIM
PCM Framing Supervision
R
:
:
Logical Ports
=1
1
0
Physical Pins:
TXD0
TSC0
RXD0
RXD1
TSC1
226
Line Drivers
& Receivers
®
Application Hints
PCM Transmission
Line #1
PCM Transmission
Line #2
PEB 2055
PEF 2055
ITD08094