PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 257
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PEB20571FV31XT
Manufacturer Part Number
PEB20571FV31XT
Description
Manufacturer
Lantiq
Datasheet
1.PEB20571FV31XT.pdf
(308 pages)
Specifications of PEB20571FV31XT
Lead Free Status / Rohs Status
Compliant
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6.2.11.9 L1_CLK Control Register
L1_CLK Control Register (CL1CLK)
Reset value: 0000
Note: ’x’ = unused bits, read as 0
.
L1CLKEN L1_CLK Disable
L1CLK
Data Sheet
15
7
x
x
0 =
1 =
L1_CLK Clock Rate
0 =
1 =
H
14
6
x
x
L1_CLK is enabled (default)
L1_CLK is disabled
7.68 MHz (default)
15.36 MHz
13
5
x
x
12
4
x
x
read/write
240
11
3
x
x
10
2
x
x
Register Description
L1CLKDIS
Address: D088
9
1
x
PEB 20570
PEB 20571
2003-07-31
L1CLK
8
0
x
H
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