ANXL1250FYC3F AMD (ADVANCED MICRO DEVICES), ANXL1250FYC3F Datasheet - Page 30

• Manufacturer Part Number: ANXL1250FYC3F
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1250FYC3F

• Lead Free Status / Rohs Status: Compliant

2.3.10
30
Signal Name
TCK
TMS
TDI
TRST#
TDO
PLLTEST#
PLLBYPASS#
PLLMON1
PLLMON2
PLLBYPASSCLK
PLLBYPASSCLK#
DBRDY
DBREQ#
SCANSHIFTEN
SCANINTEVAL
SCANCLK1
SCANCLK2
VID[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Test Measurement Interface Signals
31177H
Table 2-3. SOFTVID[4:0] and VID[4:0] Code to Voltage Definition
Pin No.
AN13
AN15
AJ25
AL13
AL15
AC3
AA1
AA3
Q1
Q3
Q5
U1
U3
U5
S3
S1
S5
V
CC_CORE
Shutdown
2.000
1.950
1.900
1.850
1.800
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
Port
O
B
O
O
I
I
I
I
I
I
I
I
I
I
I
I
i
(V)
Description
JTAG Interface Pins. TCK, TMS, TDI, TRST#, and TDO pins
should be connected directly to the circuit board debug connector.
Pull up TDI, TCK, TMS, and TRST# to V
tors.
PLL Bypass and Test. These signals makeup the PLL bypass and
test interface. This interface is tied disabled on the circuit board. All
six pin signals are routed to the debug connector. All four processor
inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and PLLMON2) are
tied to V
Debug Ready and Debug Request. DBRDY and DBREQ# are
routed to the debug connector. DBREQ# is tied to V
pull-up resistor.
Scan Interface. This interface is AMD internal and is tied disabled
with pull-down resistors to ground on the circuit board.
CC_CORE
VID[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
with pull-up resistors.
AMD Geode™ NX Processors Data Book
CC_CORE
V
CC_CORE
Shutdown
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
with pull-up resis-
Signal Definitions
CC_CORE
(V)
with a