ANXL1250FYC3F AMD (ADVANCED MICRO DEVICES), ANXL1250FYC3F Datasheet - Page 39

• Manufacturer Part Number: ANXL1250FYC3F
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1250FYC3F

• Lead Free Status / Rohs Status: Compliant

Power Management
An example of the AMD processor system bus disconnect
sequence is as follows:
1.
2.
3.
4.
5.
6.
AMD Geode™ NX Processors Data Book
The peripheral controller (Southbridge) asserts
STPCLK# to place the processor in the Stop Grant
state.
When the processor recognizes STPCLK# asserted, it
enters the Stop Grant state and then issues a Stop
Grant special cycle.
When the special cycle is received by the Northbridge,
it de-asserts CONNECT, assuming no probes are
pending, initiating a bus disconnect to the processor.
The processor responds to the Northbridge by de-
asserting PROCRDY.
The Northbridge asserts CLKFWDRST to complete
the bus disconnect sequence.
After the processor is disconnected from the bus, the
processor enters a low-power state. The Northbridge
passes the Stop Grant special cycle along to the
Southbridge.
CLKFWDRST
PROCRDY
CONNECT
STPCLK#
Figure 3-4. Exiting the Stop Grant State and Bus Connect Sequence
Figure 3-4 shows the signal sequence of events that takes
the processor out of the Stop Grant state, connects the
processor to the AMD processor system bus, and puts the
processor into the Working state.
The following sequence of events removes the processor
from the Stop Grant state and connects it to the system
bus:
1)
2)
3)
4)
The processor issues a Connect special cycle on the sys-
tem bus and resumes operating system and application
code execution.
The Southbridge de-asserts STPCLK#, informing the
processor of a wake event.
When the processor recognizes STPCLK# de-asser-
tion, it exits the low-power state and asserts
PROCRDY, notifying the Northbridge to connect to the
bus.
The Northbridge asserts CONNECT.
The Northbridge de-asserts CLKFWDRST, synchro-
nizing the forwarded clocks between the processor
and the Northbridge.
31177H
39