ANXL1250FYC3F AMD (ADVANCED MICRO DEVICES), ANXL1250FYC3F Datasheet - Page 5
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ANXL1250FYC3F
Manufacturer Part Number
ANXL1250FYC3F
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ANXL1250FYC3F.pdf
(72 pages)
Specifications of ANXL1250FYC3F
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ANXL1250FYC3F
Manufacturer:
SANSUNG
Quantity:
572
Part Number:
ANXL1250FYC3F
Manufacturer:
AMD
Quantity:
20 000
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 7-1.
AMD Geode™ NX Processors Data Book
Typical System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Processor Pin Diagram—Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Processor Pin Diagram—Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Processor Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SOFTVID Transition During the AMD Processor System Bus Disconnect for FID_Change . 37
AMD Processor System Bus Disconnect Sequence in the Stop Grant State . . . . . . . . . . . . 38
Exiting the Stop Grant State and Bus Connect Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
V
SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General ATE Open-Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Signal Relationship Requirements During Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . 61
28104 OPGA Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
OPN for the AMD Geode™ NX Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CC_CORE
Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
List of Figures
31177H
5