ANXL1250FYC3F AMD (ADVANCED MICRO DEVICES), ANXL1250FYC3F Datasheet - Page 69

• Manufacturer Part Number: ANXL1250FYC3F
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1250FYC3F

• Lead Free Status / Rohs Status: Compliant

Appendix A: Conventions, Abbreviations, and References
A.2
This section contains information about the conventions
and abbreviations used in this document.
A.2.1
• Active-Low Signals—Signal names containing a pound
• Signal Ranges—In a range of signals, the highest and
• Reserved Bits and Signals—Signals or bus bits marked
• Three-State—In timing diagrams, signal ranges that are
• Invalid and Don’t-Care—In timing diagrams, signal
A.2.2
The following list defines data terminology:
• Quantities
• Addressing—Memory is addressed as a series of bytes
• Abbreviations—The following notation is used for bits
• Little-Endian Convention—The byte with the address
AMD Geode™ NX Processors Data Book
sign, such as SFILLVALID#, indicate active-Low signals.
They are asserted in their Low-voltage state and
negated in their High-voltage state. When used in this
context, High and Low are written with an initial upper
case letter.
lowest signal numbers are contained in brackets and
separated by a colon (for example, D[63:0]).
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and
signals are reserved by AMD for future implementations.
When software reads registers with reserved bits, the
reserved bits must be masked. When software writes
such registers, it must first read the register and change
only the non-reserved bits before writing back to the
register.
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
ranges that are invalid or don't-care are filled with a
screen pattern.
— A word is two bytes (16 bits)
— A doubleword is four bytes (32 bits)
— A quadword is eight bytes (64 bits)
— An octaword is 16 bytes (128 bits)
— A cache line is eight quadwords (64 bytes)
on 8-byte (64-bit) boundaries in which each byte can be
separately enabled.
and bytes:
— Kilo (K, as in 4-Kbyte page)
— Mega (M, as in 4 Mbits/sec)
— Giga (G, as in 4 Gbytes of memory space)
xx...xx00 is in the least-significant byte position (little
end). In byte diagrams, bit positions are numbered from
right to left—the little end is on the right and the big end
is on the left. Data structure diagrams in memory show
low addresses at the bottom and high addresses at the
top. When data items are aligned, bit notation on a 64-bit
See Table A-3 for more abbreviations.
Conventions, Abbreviations, and References
Signals and Bits
Data Terminology
• Bit Ranges—In text, bit ranges are shown with brackets
• Bit Values—Bits can either be set to 1 or cleared to 0.
• Hexadecimal and Binary Numbers—Unless the context
A.2.3
Table A-3 contains the definitions of abbreviations used in
this document.
Abbreviation
A
F
G
Gb
GB
H
h
K
KB
M
Mb
MB
MHz
m
ms
mW
µ
µA
µF
µs
µV
n
nA
ns
ohm
p
pF
pH
ps
s
V
W
data bus maps directly to bit notation in 64-bit-wide
memory. Because byte addresses increase from right to
left, strings appear in reverse order when illustrated.
and a colon (for example, bits [9:1]). The same applies
for signal or bus names. The highest and lowest bit
numbers are contained in brackets and separated by a
colon (for example, AD[31:0]).
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
Table A-3. Definitions of Abbreviations
Abbreviations and Acronyms
Meaning
Ampere
Farad
Giga–
Gigabit
Gigabyte
Henry
Hexadecimal
Kilo–
Kilobyte
Mega–
Megabit
Megabyte
Megahertz
Milli–
Millisecond
Milliwatt
Micro–
Microampere
Microfarad
Microsecond
Microvolt
nano–
nanoampere
nanosecond
Ohm
pico–
picofarad
picohenry
picosecond
Second
Volt
Watt
31177H
69