UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 13

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

LVDS INTERFACE
LVDS_ADout[+,−]
LVDS_BDout[+,−]
LVDS_ADenb
LVDS_BDenb
LVDS_Synch
LVDS_TxClk
LVDS_TxPwdn
LVDS_ADin[+,−]
LVDS_ALock_n
LVDS_ARxClk
LVDS_ARefClk
LVDS_APwdn
LVDS_BDin[+,−]
LVDS_Block_n
LVDS_BRxClk
LVDS_BRefClk
LVDS_BPwdn
CPU & GENERAL CONTROL
CPU_cs
CPU_rd (CPU_ds)
CPU_wr (CPU_rnw)
CPU_int
CPU_Data[7:0]
CPU_Addr[7:0]
CPU_BusMode
GPIO [3:0]
Reset_n
JTAG TEST INTERFACE
JTAG_CLK
JTAG_Reset
JTAG_TMS
JTAG_TDI
JTAG_TDO
Test_se
TOTAL PIN COUNT
Total Functional I/O
LVDS V
CV
IOV
Total Power
No Connect
Total Pins
7.0 Signal Description
Note 1: These pins are Inputs in ATM Layer mode and Outputs PHY Layer mode
DD
DD
Signal Name
/CV
/IOV
DD
SS
/V
SS
SS
A Serial data differential outputs.
B Serial data differential outputs.
Serial transmit data A output enable.
Serial transmit data B output enable.
External control to transmit SYNCH patterns on
serial interface.
Transmit clock.
Transmit section power down
PortA Serial data differential inputs.
PortA Clock recovery lock status
PortA Recovered clock.
PortA Reference clock for receive PLLs.
PortA Power Down.
PortB Serial data differential inputs.
PortB Clock recovery lock status.
PortB Recovered clock.
PortB Reference clock for receive PLLs.
PortB Power Down.
Select signal used to validate the address bus
for read and write data transfers.
Read or Data Strobe, depending on
CPU_BusMode.
Write or Read/Write, depending on
CPU_BusMode.
Interrupt request line.
Data bus.
Address bus.
Mode select for bus protocol.
General Purpose Input/Output.
Reset min pulse is 2X slowest clock period.
Test clock.
Test circuit reset.
Test Mode Select.
Test Data In.
Test Data Out.
SCAN enable (for manufacturing test only)
3.3V LVDS power for analog and digital
2.5V Core Power for digital functions
3.3V I/O power ring
No signal connected to this pin
196 LBGA, 15x15 mm, 1.0 mm ball pitch
(Continued)
Description
TABLE 11. Pin Description (Continued)
13
Width
2
2
1
1
1
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
8
8
1
4
1
1
1
1
1
1
1
Signal Type
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BiDir
Input
Input
BiDir
Input
Input
Input
Input
Input
Input
133
196
46
60
6
8
3
Active High
Active High
Active High
Active Low
Active Low
Active Low
Active Low
Active Low
Active Low
(Write)
Active Low
Active Low
Active Low
Active High
Polarity
www.national.com
Pull Up
Pull Up
Pull Down
Pull Up
Pull Up
Pull Up
Open Drain
Pull Down
Pull Up
Pull Up
Pull Up
Pull Down
Internal
Bias