UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 49

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

ETXD2 0x12
ETXD1 0x13
ETXD0 0x14
18.0 Register Description
Type:
Software Lock: No
Reset Value:
The ETXD7, ETXD6, ETXD5, ETXD4, ETXD3, ETXD2, ETXD1 and ETXD0 registers contain the ECC message to be transmitted.
18.14 GENERAL PURPOSE INPUT OUTPUT — 0x15 GPIO
Type:
Software Lock: No
Reset Value:
The General Purpose Input/Output register controls the four general purpose input/output pins GPIO[3:0].
18.15 TEST ERROR CONTROL — 0x16 TERRCTL
Type:
Software Lock: Yes
Reset Value:
The Test Error Control register is used to control the transmission of a PRBS pattern for Bit Error Rate testing, or to introduce HEC
and BIP errors so that the Cell Delineation, Frame Delineation, Descrambler Lock and performance monitoring functions can be
tested. This is a test register and should not be used on live traffic. The exact nature of the errored HEC and BIP bytes is
determined by the ERRBIP1, ERRBIP0 and ERRHEC registers.
18.16 ERROR BIP MASK — 0x17 to 0x18 ERRBIP1 to ERRBIP0
• ETXD7–ETXD0 When the ETXBR bit is set, then these registers have full read/write access to allow flexible assembly of the
• DDR[3:0] The Data Direction bits DDR[3:0] define the function of the GPIO[3:0] pins. When a DDR bit is set the corresponding
• IO[3:0] The IO bits reflect the value of the GPIO pins. When defined as an output by the DDR bit, then the IO bit value is driven
• EBRST[3:0] The Error Burst bits EBRST[3:0] define the number of consecutive erred HEC’s and/or BIP’s to be generated and
• ERFHEC The Error Frame HEC bit, when set, will cause EBRST consecutive Frame HEC’s to be erred. When this has been
• ERCHEC The Error Cell HEC bit, when set, will cause EBRST consecutive Cell HEC’s to be erred. When this has been
• ERBIP The Error BIP bit, when set, will cause EBRST consecutive BIP’s to be erred. When this has been completed the
• TXPRBS Transmit PRBS pattern. When set, the transmit section sends the raw scrambler pseudo-random sequence
ECC message before initiating transmission by setting the ETXSD bit. When the ETXBR is clear during message transmis-
sion, these registers are read only so that the message being transmitted cannot be overwritten and corrupted.
GPIO pin is an input and when the DDR bit is clear the corresponding GPIO pin is an output.
out on the corresponding GPIO pin. When defined as an input by the DDR bit, then the IO bit value captures the incoming
value on the corresponding GPIO pin.
transmitted.
completed the hardware will clear this bit.
completed the hardware will clear this bit.
hardware will clear this bit.
(polynomial x
queue. The far end receiver can lock to this PRBS pattern to count bit errors if the RABEC/RBBEC bit is set in the
RACTL/RBCTL register. This is not a live traffic test.
EBRST[3]
DDR[3]
ETXD2[7]
ETXD1[7]
ETXD0[7]
7
7
31
Read/Write
0x00
Bits [7:4] Read/Write
Bits[3:0] are Read Only when GPIO[3:0] are defined as Inputs, and Read/Write when GPIO[3:0] are defined as
Outputs.
0xF0
Read/Write
0x00
7
+ x
28
+ 1). No data is transmitted. The TCS Assembler will be paused and no cells will be read from the FIB
EBRST[2]
DDR[2]
6
6
ETXD2[6]
ETXD1[6]
ETXD0[6]
6
EBRST[1]
DDR[1]
5
5
TABLE 33. ETXD7–ETXD0 (Continued)
ETXD2[5]
ETXD1[5]
ETXD0[5]
(Continued)
5
TABLE 35. TERRCTL
EBRST[0]
DDR[0]
TABLE 34. GPIO
4
4
ETXD2[4]
ETXD1[4]
ETXD0[4]
49
4
ERFHEC
IO[3]
3
3
ETXD2[3]
ETXD1[3]
ETXD0[3]
3
ERCHEC
IO[2]
2
2
ETXD2[2]
ETXD1[2]
ETXD0[2]
2
ERBIP
IO[1]
1
1
ETXD2[1]
ETXD1[1]
ETXD0[1]
TXPRBS
1
IO[0]
0
0
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ETXD2[0]
ETXD1[0]
ETXD0[0]
0